Interfacial charge trapping inextrinsic Y2O3/SiO2 bilayer gatedielectric based MIS devices on Si(100)

Abstract

Metal-insulator-semiconductor (MIS) structuresbased on an extrinsic Y2O3 dielectric film on Si showhigh leakage currents due to roughness-related highly localizedfields. Oxygen annealing increases the dielectric constant andstrength and reduces leakage currents by transformingY2O3 (film)/Si(100) into a bilayerY2O3 (film)/SiO2/Si(100) dielectricstructure. Evolution of interfacial SiO2 causesgeneration of mid-gap interface states at Ev + 0.23 eV and Ev + 0.43 eV, which act as electron trapsand are responsible for hysteresis effects incapacitance-voltage (C-V) andcurrent-voltage (I-V) behaviour in theaccumulation-inversion modes. The electron trappingreduces the cathodic field and causes lowering of the currentand the shift in current to higher fields after successiveramps. The charge trapping effects cause varied and unstableC-V and I-V behaviour of MIS structures based on a Y2O3/SiO2 bilayer gate dielectric. Its origin hasbeen attributed to microstructure and defect state modificationat the Y2O3 film-Si interface. This limitsits application in high-density dynamic random access memory andultra-large-scale integration devices.