High Mobility Channel Research Articles

Path Loss Measurement Validation Using Naïve Bayes Classification for High-Speed Rail

This work proposes path loss measurement validation for high-speed rail wireless communication using Naïve Bayes Classification Method. Path loss propagation model is a major component in wireless network planning in order to meet expected service level requirements and optimized cell towers distribution. However, path loss in high-speed rail propagates rapidly because of unexpected environmental shifts, high mobility, and unique channel modelling. All these unique characteristics lead to inaccuracies and uncertainties in the path loss measurement. Naïve Bayes Classification with Gaussian Classifier offers a better solution in validating path loss measurement than the conventional method for typical wireless communication, which provides statistical descriptions of site-specific environments. The measurement dataset has been taken as continuous values and it is assumed to be distributed according to normal distribution. The dataset has been collected from a running high-speed train. Data discretization has been used as a pre-processing step of transforming continuous data attribute values into a finite set of intervals consisting of path loss in maximum and minimum speed for accuracy or inaccuracy class. The satisfying result of the best performance has been obtained in Accuracy Value (0.9114), Precision Value (0.9147), Recall Value (0.8772), F1-score (0.8956), and Area Under Curve score (0.83). The results have shown that the Naive Bayes method can potentially replace the conventional method in validating path loss measurement, especially for high-speed rail.

(Invited) Layer Transfer Technology for Stacked Multi-Channel Semiconductor-on-Insulator Platform

Continuous scaling of device dimension pushed Si channel to its physical limit, alternative high mobility channels such as (Si)Ge and (In)GaAs have been considered to replace Si to further enhance CMOS performance. In the meantime, ultrathin body (UTB) semiconductor-on-insulator is compulsory structure for improved gate control and immunity against short channel effects in the ultimately scaled high performance and low power dissipation CMOS. To realize stacked multi- channel semiconductor-on-insulator platform on current mainstream Si wafers, layer transfer technology [1-3] utilizing direct bonding and selective etching was developed to integrate (Si)Ge or (In)GaAs channels on Si, showing great potential for ultimate device structures with heterogeneous integration.Figure 1(a) is the process flow for integrating InGaAs channel onto SiGe-on-insulator (SGOI) structure utilizing layer transfer technology [4]. It started with bottom SGOI pMOSFET fabrication. The SGOI structure was realized by 2-step Ge condensation technique, resulting in Ge content of 70%. After high k metal gate process, self-aligned Ni-SiGe alloy was formed as S/D metal. Subsequently, SiO2 interlayer was deposited by CVD, followed by CMP planarization. Then, InGaAs grown on InP was directly bonded onto SiO2 and InP substrates were selectively etched away. Finally, the top InGaAsOI nMOSFET fabrication and metal interconnection completed the CMOS fabrication. Fig. 1(b) shows the cross-sectional TEM images of fabricated InGaAs/SiGe channel stacked CMOS. Well aligned top and bottom devices are seen without any distinct defects.Figures 2 is a schematic flow for fabricating Ge/Si double channel-on-insulator structure by low temperature hetero-layer bonding technology (LT-HBT). The technology starts with the preparation of donor wafers (Fig. 2(a)) for the top Ge channel layer and host wafers (Fig. 2(b)) for the bottom Si channel layer. For donor wafers, a 200-nm-thick Ge was epitaxially grown on SOI wafer by reduced pressure CVD. After CMP planarization, ALD SiO2 is deposited onto Ge. For host wafers, implantation and dopant activation were carried out, followed by chemical treatment for Si oxidation. After surface activation by room temperature chemical treatment (Fig. 2(c)), the direct wafer bonding of both SiO2 surface was performed at 200 °C in a press machine (Fig. 2(d)). Then, the Si substrate of the donor wafer was removed with deep RIE. At this time, the BOX layer of the donor wafer serves as an etch-stop layer. Subsequently, the BOX layer and thin Si layer of the donor wafer were removed selectively in HF and TMAH solution, respectively (Fig. 2(f)). To precise control the top Ge channel thickness, a series of low damage etching process was adapted to thin down Ge (Fig. 2(g)). The realized double channel structure is fully isolated with an insulating insertion layer,[5] which is very promising for realizing novel complementary FET (CFET) with minimum process steps. The cross-sectional TEM image of Ge/Si stacked channel of CFET after high k metal gate process is demonstrated in Fig. 2(h). Even more multiple stacks can be realized by using LT-HBT. A vertically stacked three-layer structure with 2 bottom Si layers and 1 top Ge layers is also demonstrated using SOI-based donor wafers in Fig. 3, indicating the highly integrated density channel structure is possible. The feasibility of layer transfer technology has been proved for multi-channel structure with high mobility channels for N2 node and beyond. Acknowledgement This work was supported by JST Japan-Taiwan Collaborative Research Program, Grant Number JPMJKB1902, Japan and the Ministry of Science and Technology under Grant Number MOST-109-2628-E-492-001-MY3, 109-2923-E-492-001-MY3, 107-2221-E-492-016-MY3.

(Invited) Electrical Performance Improvement in 300mm Ge-Based Devices

As device feature size continues to scale, new device architecture and dielectric materials with engineered properties are becoming essential in overcoming the issues in scaled CMOS devices such as short channel effects. Some of the recent innovations device makers are exploring for better electrostatic control and improved performance are the introduction of new device architecture such as gate all around devices (nanowires/nanosheets), and channel engineering such as high mobility channel materials (Ge and III-V). Ge is particularly attractive for use as a channel material for P-type MOSFETs due to its high hole mobility and Si VLSI high volume manufacturing (HVM) compatibility. However, there are couple significant remaining challenges to integrating Ge into 300mm Si VLSI HVM which are a stable gate-stack formation and integration of Ge on Si (1-5). In this talk, advances in Ge gate stack engineering will be discussed. Using Si compatible technologies we have demonstrated scaled EOT by engineering both the interface and high-k formation. Reference Swaminathan, Y. Oshima, M. Kelly, P.C. McIntyre, Appl. Phys. Lett., 95, 032907 (2009).Zhang, M. Gunji, S. Thombare, P.C. McIntyre, IEEE Electr. Device. L., 34, 736 (2013).H Lee, T. Nishimura, C. Lu, S. Kabuyanagi, A. Toriumi, IEDM, 32.5.1 (2014).S. Goley, M. K. Hudait, Materials, 2301 (2014).Xie, S. Deng, M. Shaekers, D. Lin, M. Caymax, A. Delabie, X-P Qu, Y-L. Jiang, D. Dedytsche, C. Detavernier, Semicond. Sci. Technol. 074012 (2012)

(Invited) Interface Treatment Related Defects During Ge Gate Stack Formation

Germanium as a high mobility channel material is currently of considerable interest since Ge has both higher electron and hole mobility as compared to silicon (1). The deposition of high-k dielectrics on Ge has been a significant challenge because of high interface defects density, Dit (2). By considering the interface reaction kinetics, thermal budget various atomic layer deposition (ALD) schemes and interface treatments can be identified to get a stable dielectric with a robust interface. However, understanding of the interface kinetics and defect distribution into gate stack and/or Ge is still limited.In this work, we report the impact of different interface treatments on the p type Ge prior to any high-k layer deposition on defect generation. Ge surface was oxidized by a controlled chemical oxidation, slot-plane-antenna plasma oxidation and oxidation through vapor O3 treatment before ALD deposition of 1nm Al2O3/3.5nm ZrO2 for gate stack formation. These devices were characterized to evaluate the interface and possible bulk defects by deep level transient spectroscopy (DLTS), capacitance spectroscopy, conductance method in addition to standard I-V and C-V measurements. DLTS has the advantage to have the spectrum comparison among the interface treatments. Signature of these spectra can reveal the difference, which is more accurate than the defects estimated by Conductance method. DLTS also provides the signature of slow traps (~1ms) (Fig. 1) originating from the bulk or interface depending on the type of GeOx formation.Furthermore, we evaluate the defect distribution when the gate stack was subjected to a slot-plane antenna plasma oxidation prior to metal deposition. A TiN/Hf1-xZrxO2/Al2O3/Ge gate stack with six different Zr content was investigated (Fig. 2). Al2O3 was used to impede the Ge diffusion into the gate stack. Interface state density (Dit) and C-V hysteresis show that the mid-gap Dit tend to increase with decrease in EOT, possibly due to the undesirable native oxide formation on Ge.The author would like to thank Drs. Y.M. Ding (Western Digital Corporation, Shanghai, China), M.N. Bhuyian (Globalfoundries, Malta, NY, USA), K.L. Ganapathi (Indian Institute of Technology Madras, India), N. Bhat, (Indian Institute of Science, Bangalore, India) and K. Tapily, R. D. Clark, S. Consiglio, C. S. Wajda, G. Nakamura, and G. J. Leusink of TEL Technology Center, America, Albany, NY, for their help in this work. References Arimura et al, IEDM Technical Digest, (2020)N. Bhuyian et al, ECS Journal of Solid-St. Sci. and Tech., vol. 7(2), N1-N6, (2018)G. Kolla et al, J. Vac. Sci. Technol. B, 36(2), 021201 (2018)Ding et al, IEEE Trans. on Dev. and Materials Reliability, 17(2), 349-354, (2017)Ding, et al, J. of Vac. Sci. and Technol. B, 34(2), 021203, 2016. Figure 1

(Invited) Defect Engineering for Monolithic Integration of III-V Semiconductors on Silicon Substrates

Implementation of high-mobility channel materials enables to increase the device performance due to the higher carrier mobility compared to silicon devices. III-V based materials such as GaAs and ternary systems (e.g. InxGa1-xAs alloys) are achieving high performing n-channel transistors. The strong progress in hetero-epitaxy using nano ridge engineering [1] leading to monolithic heterogeneous integration of III-V materials on silicon substrates resulted in state-of-the-art FinFETs, gate-all-around (GAA) and horizontal or vertical stacked nanowires (NW) on 300 mm Si wafers [2,3]. Very promising results have also been reported for GaN on Si triggering their use for high power and RF applications [4].One of the main challenges remains a good defect control in order not to degrade the electrical performance of devices and circuits [5]. The nucleation of extended defects is directly related to the hetero-epitaxial growth of layers with a lattice mismatch and their concentration depends on the composition of the layers such as e.g. the In content in InxGa1-xAs and the Al content in AlxGa1-xN. The defects have a direct impact on the generation and recombination lifetime and the leakage current [5], while also the low frequency noise (LFN) performance is influenced [6]. The identification of the defects (energy level ET, capture cross section and concentration) can be determined using Deep Level Transient Spectroscopy (DLTS) and low frequency noise spectroscopy by measuring LFN as a function of temperature.The goal of this work is to review the knowledge about defect engineering and to analyze the electrical activity of extended defects in III-V semiconductors on silicon substrates. Different case studies will be used to illustrate both the defect identification and the electrical activity of the defects. The impact of the used processing schemes to fabricate the devices is also discussed. It will e.g. be shown that defects in GaN/AlGaN MOSHEMTs increase the low frequency noise due to generation-recombination centers in the GaN depletion layer [7]. These traps can lead to a distortion of the current-voltage characteristics of short channel devices. DLTS studies are a powerful tool to identify traps and to investigate their impact on the leakage current of III-V on Si devices. Double correlation DLTS investigations on GaAs/InGaP/GaAs diodes pointed out that traps associated with sidewall interface states can dominate the peripheral diode leakage current. The focus of the presentation will be on the current understanding of defect engineering associated with the monolithic integration of III-V materials on Si and a discussion of recent results concerning the electrical activity of the defects and the defect modeling.[1] M. Baryshnikova et al., Crystals, 10, 330 (2020).[2] X. Sun et al., Digest VLSI Technology, T3-4 (2017).[3] A.P. Milemin et al., Microelectron. Eng., 192, 14 (2019).[4] L. Li et al., IEEE Electron Device Lett., 41, 689 (2020).[5] C. Claeys et al., ECS Solid State Electronics, 9, 03301 (2020).[6] C. Claeys et al., J. Phys. Cond. Ser., 1190, 012001 (2019).[7] K. Takakura et al., IEEE Trans. Electron Dev., 67, 3062 (2020).

(Invited) Layer Transfer Technology for Stacked Multi-Channel Semiconductor-on-Insulator Platform

Continuous scaling of device dimension pushed CMOS technology based on Si materials to its physical limit, alternative high mobility channels such as (Si)Ge and III-V materials have been considered to replace Si to further enhance CMOS performance. In the meantime, ultrathin body (UTB) semiconductor-on-insulator is attractive for fabricating nanowire/nanosheet channel structures for improved gate controllability and immunity against short channel effects in the ultra-scaled high performance and low power dissipation CMOS. To realize multiple channels stacked semiconductor-on-insulator platform on current mainstream Si wafers, layer transfer technology utilizing direct bonding and selective etching was developed to integrate UTB (Si)Ge or InGaAs channels on Si. The devices fabricated with multiple stacked nanowire/nanosheet channels have also been demonstrated through sequential or monolithic 3D integration approach, showing great potential of layer transfer technology for ultimate CMOS structures.

7‐3: Invited Paper: High Mobility Self‐Aligned Coplanar Thin‐Film Transistors with a Novel Dual Channel Oxide Semiconductor Architecture

Self‐aligned coplanar thin‐film transistors (TFTs) with a novel dual channel architecture comprising of low mobility and high mobility oxide semiconductors show high field‐effect mobility of > 50 cm2/Vs with positive threshold voltage of > 0 V and low off‐leakage current of < 1 pA. The TFTs with dual channel allow higher mobility than TFTs with a single high mobility channel because the TFTs with dual channel allow strong electron accumulation due to high electron densities both at the interface between gate insulator and 1st oxide semiconductor and at the hetero‐junction interface between 1st and 2nd oxide semiconductors.

A Comprehensive Benchmarking Method for the Net Combination of Mobility Enhancement and Density-of-States Bottleneck

In this letter, we propose a comprehensive benchmarking method to simultaneously address mobility enhancement and density-of-states bottleneck in advanced field-effect-transistors (FETs) with novel high-mobility (high-μ) channel materials, where we focused on conventional covalent bonding semiconductors with pure and partially ionic character. This method relies only on the measured extrinsic transconductance of a long-channel FET in the saturation regime together with the source resistance, yielding the product of the effective mobility ( μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) and effective gate capacitance ( C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_eff</sub> ). We tested this method in In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> As quantum-well high-electron-mobility transistors (HEMTs) with various indium mole fractions, such as 0.53, 0.7, 0.8 and 1, as well as in Si n-FETs. We found that the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> As HEMTs with μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> over 10,000 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s at 300 K provided more than 20 times greater μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ×C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_eff</sub> than Si n-FETs. More specifically, the product initially improved as x increased, then showed a peak value of 10,300 μF·V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ·s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> at x of around 0.8, and degraded slightly beyond that composition. To verify the validness of the proposed method, we separately measured and analyzed C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_eff</sub> and μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> using the split-CV technique, showing excellent agreement with the ones from the proposed method.

Monolithic integration of ultraviolet light emitting diodes and photodetectors on a p-GaN/AlGaN/GaN/Si platform.

In this letter, we report the first demonstration of monolithically integrated ultraviolet (UV) light emitting diodes (LEDs) and visible-blind UV photodetectors (PDs) employing the same p-GaN/AlGaN/GaN epi-structures grown on Si. Due to the radiative recombination of holes from the p-GaN layer with electrons from the 2-D electron gas (2DEG) accumulating at the AlGaN/GaN heterointerface, the forward biased LED with p-GaN/AlGaN/GaN junction exhibits uniform light emission at 360 nm. Facilitated by the high-mobility 2DEG channel governed by a p-GaN optical gate, the visible-blind phototransistor-type PDs show a low dark current of ∼10-7 mA/mm and a high responsivity of 3.5×105 A/W. Consequently, high-sensitivity photo response with a large photo-to-dark current ratio of over 106 and a response time less than 0.5 s is achieved in the PD under the UV illumination from the on-chip adjacent LED. The demonstrated simple integration scheme of high-performance UV PDs and LEDs shows great potential for various applications such as compact opto-isolators.

The past and future of multi-gate field-effect transistors: Process challenges and reliability issues

This work reviews the state-of-the art multi-gate field-effect transistor (MuGFET) process technologies and compares the device performance and reliability characteristics of the MuGFETs with the planar Si CMOS devices. Owing to the 3D wrapped gate structure, MuGFETs can suppress the SCEs and improve the ON-current performance due to the volume inversion of the channel region. As the Si CMOS technology pioneers to sub-10 nm nodes, the process challenges in terms of lithography capability, process integration controversies, performance variability etc. were also discussed in this work. Due to the severe self-heating effect in the MuGFETs, the ballistic transport and reliability characteristics were investigated. Future alternatives for the current Si MuGFET technology were discussed at the end of the paper. More work needs to be done to realize novel high mobility channel MuGFETs with better performance and reliability.

Mobility enhancement techniques for Ge and GeSn MOSFETs

The performance enhancement of conventional Si MOSFETs through device scaling is becoming increasingly difficult. The application of high mobility channel materials is one of the most promising solutions to overcome the bottleneck. The Ge and GeSn channels attract a lot of interest as the alternative channel materials, not only because of the high carrier mobility but also the superior compatibility with typical Si CMOS technology. In this paper, the recent progress of high mobility Ge and GeSn MOSFETs has been investigated, providing feasible approaches to improve the performance of Ge and GeSn devices for future CMOS technologies.

Mobility improvement of 4H-SiC (0001) MOSFETs by a three-step process of H2 etching, SiO2 deposition, and interface nitridation

4H-SiC(0001) metal-oxide-semiconductor field-effect transistors (MOSFETs) and MOS capacitors were fabricated by the following procedures: H2 etching, SiO2 deposition, and nitridation, and their electrical characteristics were evaluated. Substantially low interface state densities (4–6 × 1010 cm−2 eV−1) and high channel mobilities (80–85 cm2 V−1 s−1) were achieved by N2 annealing or NO annealing after H2 etching and SiO2 deposition. The threshold voltage of the MOSFETs fabricated with N2 annealing was shifted negatively when the oxide was formed by deposition. On the other hand, normally-off operation and high channel mobility were compatible for the MOSFETs fabricated with NO annealing.

A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V MIN Applications

A 135-Mb 0.021- $\mu \text{m}^{2}$ 6-T high-density SRAM bit cell with write-assist circuitries was successfully implemented by using 5-nm HK-metal gate FinFET with EUV and high-mobility channel (HMC) technology. This article proposes the metal capacitor coupling negative bitline (NBL) and the charge-sharing lower cell-VDD (CS-LCV) write-assist techniques to reduce the SRAM minimal supply voltage. Flying bitline (FBL) architecture is also implemented to improve the high-density SRAM macro-bit density by 5%. Silicon data show that both NBL and LCV write-assist techniques can improve the overall SRAM minimal supply voltage performance by more than 300 mV at the 95th percentile.

Neighbor Discovery for ProSe and V2X Communications

Device-to-Device (D2D) communication underlying cellular networks was first introduced in the 3GPP Rel. 12 specifications, and was initially referred to as proximity services (ProSe). Its primary aim was to serve billions of Internet of Things (IoT) devices for 5G and beyond-5G networks. To enable D2D link establishment between various user equipments (UEs), the neighbor discovery process became crucial. This article investigates neighbor discovery for ProSe and Vehicle-to-Everything (V2X) communications through a SideLink interface, which is specifically introduced to support D2D communications over cellular networks. A single-user scenario is first considered to derive the probability of discovery in its closed-form and compare it with simulation results to validate its theoretical analysis. This scenario employs the demodulation reference signal (DMRS), where a power-normalized-correlation (PNC)-based metric is performed to determine the presence of active peers in the vicinity. Moreover, a multiuser scenario is considered to assess the impact of interference on the discovery probability in the cases of low and high vehicular mobility channel models. Then, group discovery is investigated using two strategies: 1) a distributed scheme incorporating out-of-coverage communications (modes 2 and 4) or 2) a network-assisted scheme applicable for supervised communications (modes 1 and 3). In this study, discovery periods are modeled as an Aloha-like protocol in the first case and a Polling-like protocol in the second case with either MAC layer or PHY layer collision models. Simulations are performed to evaluate the time required for group discovery completion as well as the collision rate in both low-mobility and high-mobility channels.

Formation and Evaluation of Al2O3 Layer By Direct ALD on Epitaxial SiGe

In recent years, SiGe and Ge have drawn considerable attention as a high mobility channel material toward next-generation complementary metal-oxide-semiconductor (CMOS) circuits. In particular, by inducing strain into Ge using Ge/SiGe hetero-structure, highly enhanced mobility which greatly exceed the bulk mobility have been reported [1]. In order to obtain high mobility, it is necessary to generate larger strain. As one of the methods, strained SiGe on Ge-on-Si is expected. In addition, in order to realize a high mobility SiGe channel MOSFET, it is necessary to form the high-quality gate stacks and interfaces between a gate insulator film and a SiGe surface. In fact, the use of atomic layer deposition (ALD) or plasma oxidation has provided a high quality interface between Ge and the insulator film [2, 3]. However, unlike Si, wet cleaning of Ge or hydrofluoric acid treatment does not provide a high-quality hydrogen-terminated surface, and there is concern about surface oxidation and impurity adsorption. Therefore, we have attempted direct ALD on epitaxially grown Ge and reported that the Ge/Al2O3 interface properties are improved [4]. In the case of SiGe, a high-quality hydrogen-terminated surface cannot be obtained by wet cleaning or hydrofluoric acid treatment. For this reason, oxidation or impurity adsorption on the SiGe surface is feared. In this study, for the application to strained SiGe channel MOSFET, an Al2O3 film was formed using ALD on epitaxially grown SiGe as a gate stack structure on SiGe, and the interface structure was evaluated.Two types of samples were prepared by two methods. An n-type Ge (100) substrate was used in this study. The Ge substrate was chemically cleaned with NH4OH solution and followed by a HF dip and de-ionized water rinse. The wet-cleaned Ge substrate was loaded into an MBE chamber and subjected to thermal cleaning at 600 °C for 10 min. Subsequently, a 50 nm thick SiGe layer (called epi-SiGe hereafter) was hetero-epitaxially grown on the Ge substrate at 300 °C. The as-grown sample was subsequently transferred to the vacuum-connected ALD chamber and an Al2O3 film was deposited by ALD (Sample (A)). For comparison, after the epitaxial growth of the SiGe, the sample was once taken out from the chamber and exposed to the atmosphere for 5 min. The sample was then reloaded into the ALD chamber and an Al2O3 film was deposited (sample (B)). ALD of Al2O3 films was carried out for 20 cycles with precursors of TMA and H2O at a substrate temperature of 300 °C. Chemical bonding states were examined by x-ray photoelectron spectroscopy (XPS) using an ESCA-300 manufactured by Scienta Instruments AB.According to figs.1 (a) and (b), it was confirmed that the GeOx peak of the sample (A) transferred in a vacuum was significantly smaller than that of the sample (B) once exposed to the atmosphere. In particular, almost no Ge4+ peak [5] arising from Ge in GeO2 was observed, indicating that oxidation of Ge was suppressed by transport in vacuum. It is considered that the GeOx peak in the sample (A) is derived from the interface between Al2O3 and SiGe. According to figs.1 (c) and (d), no Si4+ component (binding energy range 102eV to 104eV) is found in the Si 2p 3/2 spectrum of the sample (A) transferred in a vacuum. In summary, XPS analyses reveal that formation of GeO2 and SiO2 by natural oxidation can be almost avoided by ALD on the epitaxial SiGe, and it is indicated that the Al2O3/SiGe interface created does not contain the interfacial GeO2 layer which is present for the sample exposed to the air before ALD. These results clearly indicate that the direct ALD on epitaxial SiGe is very promising way to highly improve the SiGe MOSFET performances.AcknowledgmentsThis work was partly supported by the MEXT Supported Program for the Strategic Research Foundation at Private Universities 2015–2019, a Grant-in-Aid for Scientific Research from MEXT and Interdisciplinary Research Center for Nano Science and Technology in Tokyo City University.

(Invited) Epitaxial Growth of Ge/III-V Films and Hetero-Layer Lift-off for Ultra-Thin GeOI Fabrication

Monolithic 3D (M3D) integration has been thought of as an attractive idea to realize multi-functional heterogeneous integration devices. M3D integration enables us to combine logic devices with different functional devices such as memory, sensor, or optics to create extremely compact and efficient system-on-chips. Ge and III-V compound semiconductors are expected to be implemented as high mobility channel materials and optical components which cannot be realized with Si. The layer transfer technique with low processing temperature has great potential for stacking non-lattice-matched crystalline materials for M3D ICs. Here, we discuss the layer transfer technology utilizing high quality epitaxial growth, low-temperature direct bonding and advanced epitaxial lift-off (ELO) process, which reveals the applicability of transferred layers for heterogeneous integration.The low temperature ELO process is essential for realizing reliable layer transfer with different materials because the process is almost free from the issues of thermal expansion mismatch. Process flow of GaAs or Ge layer transfer with ELO process is described in Fig. 1. First of all, a lattice-matched single crystal GaAs or Ge layer is epitaxially grown on GaAs substrate with an AlAs release layer by MOCVD. Subsequently, Al2O3 layer is deposited on the epitaxial layer by atomic layer deposition (ALD). ALD Al2O3 layer serves as the buried oxide (BOX) and the passivation layer for Ge or GaAs surface. Then, Ge or GaAs layer is patterned using photolithography. The patterned GaAs or Ge/AlAs/GaAs donor wafer is then bonded on host substrate by direct bonding technique with wet activation process. Finally, the epitaxial GaAs or Ge layer is transferred on host substrates by splitting GaAs donor wafer from AlAs layer with HCl side etching thanks to extremely high etching selectivity. Note that the fabrication of patterned transfer layer is effective in shortening the required time of ELO process. In this ELO process, the thickness of a transferred layer can be control by epitaxial layer thickness. After the layer transfer process, the released donor GaAs wafer can be reclaimed and reused for the subsequent re-epitaxial growth to reduce the process cost.Figs. 2 (a) and (b) show cross-sectional SEM and TEM images of fabricated GeOI substrate with different BOX structures. Ge pattern edge shows no peeling from SiO2(100nm)/Si substrate, indicating strong bonding strength at the pattern edge. In Fig. 2 (b), the bonding interface is clearly observed at Al2O3(5nm)/SiO2(50nm) interface formed by the wet activation process. The bonding interface exhibits very smooth and no defect. There is no observable defect in transferred Ge layer, suggesting dislocation density is below TEM detection limit. Compared to Smart-CutTM technique, ELO process has significant advantages in terms of crystal quality, thickness control and the surface flatness thanks to totally low temperature processing.To reduce wafer-scale thickness variation, etching stopper (ES) technique with high etching selectivity is quite useful. As a donor wafer, we prepare Ge active layer (20nm)/SiGe ES layer (5nm)/Ge buffer layer/AlAs/GaAs structures. Here, the SiGe layer serves as ES against the etching of Ge buffer layer to control the final GeOI thickness and attain the wafer-scale thickness uniformity. In addition, Si passivation on Ge surface was performed during initial epitaxial growth of donor wafer since Si passivation was proved to be effective in reducing interfacial trap density (D it) between Ge and oxide. After ELO process, Ge buffer layer /SiGe ES layer/Ge active layer / Al2O3 /SiO2/Si heterostructure was obtained. Then, the top Ge buffer layer was removed in HCl/H2O2 solution. We found the etching selectivity was more than 30 between Ge and SiGe layer, which is high enough to yield very smooth SiGe surface. Finally, SiGe layer was removed by TMAH preferentially.Further conformal thinning of Ge active layer was performed by the cyclic dry oxidation/wet digital etching (DE) at room temperature. In addition to thickness control with the etching rate of about 0.8 nm/cycle, it is found that dozens digital etching (DDE) process is effective for reducing Ge surface roughness. Finally, UTB GeOI substrates with high crystal quality down to 3 nm have been successfully fabricated through SiGe ES and DDE processes. Ultra-smooth GeOI surface with reduced thickness fluctuation was confirmed after DDE by TEM cross-sectional images, resulting in significant improvement of device performances. Figure 1

(G03 Best Paper Award Winner) Si-Passivated Ge Gate Sacks with Low Interface State and Oxide Trap Densities Using Thulium Silicate

Germanium is considered as a high mobility channel material for its potential to be introduced in future CMOS technology nodes. Ge surface passivation with a thin silicon layer (Si-cap) has been shown to be efficient for pFETs because of a sufficient valence band offset between Ge and Si-cap, which confines the holes in the Ge layer. Strained Ge pFinFETs outperforming Si pFinFETs due to four times higher mobility have been demonstrated using Si-cap process [1]. Interfacial defects can be further passivated with a high-pressure anneal in H2 resulting in reduced sub-threshold swing and increased mobility in Ge nanowires [2]. Moreover, by using a Si-cap, Negative-bias temperature instability reliability is improved compared to GeOx passivation because of the energy decoupling between holes and defects in SiO2/HfO2 gate stack [3]. However, a Si-cap process poses gate stack scalability issues because in order to achieve sufficient surface passivation, the Si-cap thickness cannot be scaled. An introduction of a high-k interfacial layer instead of a chemical oxide SiO2 could potentially help to scale down equivalent oxide thickness. Integrating thulium silicate (TmSiO) as a replacement of the SiO2 interfacial layer has been demonstrated on silicon, and a hole and electron mobility enhancement compared to SiO2/HfO2 gate stacks has been achieved for an equivalent oxide thickness (EOT) < 1 nm [4]. Moreover, we have previously displayed the compatibility of Tm2O3 with Ge by demonstrating GeOx/Tm2O3 gate stacks with interface state density Dit < 5·1011 eV-1cm-2 [5]. In this work, we integrate TmSiO with a Si-cap process to achieve Dit comparable to GeO2 passivation.In order to evaluate Ge/Si/TmSiO interfaces, MOS capacitors (MOSCAPs) were fabricated on n-type Ge strain relaxed buffers epitaxially grown on n-type Si wafers in a two-step process using GeH4 precursor [6]. Si-caps of different thicknesses were grown at 400 °C using Si2H6. Si growth was confirmed by ellipsometry spectroscopy and testing that the surface is hydrophobic. While trying to keep the Si-cap exposure to air to a minimum, 400 nm PECVD SiO2 was deposited and active areas were defined. After removing the remaining SiO2 from the active areas with 1 % HF, Tm2O3 was deposited by atomic layer deposition (ALD) at 225 °C. Rapid thermal anneal at 550 °C for 60 s in N2 was then employed to form TmSiO layer. High-k HfO2 was deposited by ALD at 350 °C followed by a post deposition anneal in O3 for 10 min. TiN gate metal was deposited at 425 °C by ALD and 500 nm Al was deposited by sputtering for probing purposes. After patterning, the samples were subjected to a forming gas anneal of 10% H2 in N2 at 400 °C for 30 min. Reference MOSCAPs with Ge/GeOx/Tm2O3/HfO2 gate stacks were also fabricated as described in [5] with addition of ALD HfO2.Interface state density in the midgap of Ge/Si/TmSiO/Tm2O3/HfO2 gate stacks was evaluated by CV measurements where measured CV characteristics where compared to calculated ones assuming a parabolic Dit distribution. Dit highly depends on Si-cap thickness, as displayed in Fig. 1. An optimal Si-cap thickness corresponding to 40-50 min deposition time provides Dit at midgap ~5·1011 cm-2eV-1 at CET of 4 nm. Reference MOSCAPs with Ge/GeOx/Tm2O3/HfO2 gates exhibit similar Dit of 4-5·1011 cm-2eV-1. Interface state density distribution within the band gap of Ge/Si/TmSiO interface with 40 min Si-cap deposition time was evaluated using the conductance method at different temperatures and is displayed in Fig. 2. Dit in the midgap is in agreement with the results obtained from CV measurements, and increases towards the valence and conduction band edges. The oxide trapped charge Qox of 2.5·1010 cm-2 (40 times lower than in the Ge reference devices without Si-cap) was determined from CV measurements and corresponds to only 5 mV hysteresis showing the potential of superior reliability.A Si-cap process with high-k TmSiO interface has been demonstrated on Ge MOS devices. A low Dit comparable to GeOx passivation has been shown. In addition, devices with TmSiO potentially have a superior reliability vs GeOx devices due to low oxide trapped charge density.

Vertically Stacked High Mobility GeSi nGAAFETs

Si FinFET architecture has been used in mass production in the industry for advanced technology nodes. Thin and tall fin for high drive current is needed for further scaling by FinFETs. However, fin aspect ratio and lithography limitation may be problematic issues. Recently, vertically stacked channel GAAFETs become good candidates to achieve better power-performance properties than FinFETs for the given footprint. The evolution to the stacked GAAFETs mitigates the patterning challenges by well-controlled epitaxy and high etching selectivity to achieve high performance and good electrostatics. The state-of-the-art stacked Si channel n/pGAAFETs and stacked Ge channel pGAAFETs have been reported. In this study, we demonstrate vertically stacked tensily strained GeSi nGAAFETs. The stacked GeSi nGAAFETs provide a possible solution to achieve high performance and to improve the electrostatics for Ge-based channel GAAFETs.The Ge/Ge0.85Si0.15 and Ge/Ge0.98Si0.02 multilayers are epitaxially grown on SOI substrates by CVD epitaxy. Ge buffer layers and sacrificial layers are not only used to achieve etching selectivity over GeSi layers to form the vertically stacked GeSi channels, but also used to provide tensile strain for GeSi n channels. Undoped channels and heavily doped sacrificial layers are used to reduce the impurity scattering and S/D resistance, respectively. The following PMA, laser annealing, and NiGe contacts formation for nFETs can further reduce the parasitic resistance to reveal the intrinsic merit of the high mobility GeSi channels.For GeSi nFETs, [Ge] larger than 85% in GeSi can ensure L valley conduction for small conductive effective mass to achieve high mobility. The △Ec between GeSi and Si is nearly zero and can be negligible. As a result, electron can flow through stacked GeSi channels and Si channel underneath for the nFETs. An engineering solution is provided to improve the electrostatic behaviors of Ge-based channels GAAFETs. We demonstrate the vertically stacked Ge0.85Si0.15 channels above a Si channel, which has good subthreshold behaviors. The VT difference between Ge0.85Si0.15 and Si can be tuned by the channel size optimizing. By narrowing the Ge0.85Si0.15 channel size to 5nm, the bandgap can be increased by quantum confinement and the short channel effect can be suppressed. As a result, more positive VT for Ge0.85Si0.15 than Si is observed. Therefore, the underneath Si channel with good electrostatic turn on first and dominate the subthreshold region. Good SS=76mV/dec and low DIBL=36mV/V are obtained due to low Dit and good short channel control. IOFF is also dramatically reduced and the ION/IOFF is improved to be 1.2E7 thanks to the increase of the bandgap and the improved short channel control for the narrow Ge0.85Si0.15 channels. The improved flicker noise of optimized channel size also indicates the enhanced reliability.To increase [Ge] in channel layers for mobility enhancement, Si incorporation as small as 2% into Ge can achieve sufficient etching selectivity of heavily phosphorus-doped Ge sacrificial layers over undoped Ge0.98Si0.02 to form two stacked Ge0.98Si0.02 nanowire channels, and introduce 0.27% uniaxial tensile strain for the electron mobility enhancement. The alloy scattering is still minimal for 2% Si. An additional 800oC anneal after the Ge buffer growth further improves the epi quality by confining misfit dislocations near the Ge buffer/Si interface. However, the Dit at Si underneath channel/dielectrics interface may be poor due to misfit dislocations confinement. As a result, the parasitic Ge/Si channel underneath the Ge0.98Si0.02 channels is completely removed by optimized etching. The distinct photoresponse of the floating channels and the parasitic channels can be a signature and provide a non-destructive method to check the existence of the parasitic channels. The photoresponse of the sole parasitic channel mainly shows the photocurrent (Iph), while the photoresponse of the sole floating channels without parasitic channel yields the negative threshold voltage shift (ΔVT) for nFETs. The device with both floating channels and the parasitic channel shows both photocurrent and negative threshold voltage shift under exposure. ION can be enhanced by scaled LG and large channel cross section. Record ION of 48μA per stack at VOV=VDS=0.5V and record Q (Gm,max/SSSAT) of 8.3 at VDS=0.5V with LG=40 nm are achieved among Ge nFETs.CVD grown Ge nGAAFET is compatible with Si technology. Excellent electrical characteristics are achieved and the results are comparable to mature Si nFETs. Indicating vertically stacked high mobility channel is promising candidate for CMOS applications in the future technology nodes to further extend the Moore’s law.Acknowledgements: This work is supported by MOST (MOST 109-2218-E-002-031- and 108-2622-8-002-016-) and MOE (NTU-CC-109L891601), Taiwan. The support from Taiwan Semiconductor Research Institute is also highly appreciated.

(Invited) Si-Cap-Free Low-DIT SiGe Gate Stack for High-Performance pFETs

As the continuous physical device scaling is facing increasing challenges in today’s CMOS technology, introduction of high mobility channel material has further increased its potential value as performance booster. Low-Ge-content SiGe is the leading candidate for p-channel devices, as it is process-compatible with state-of-the-art Si CMOS fabrication platform and requires no strain relaxed buffer layer. In order to benefit from the high intrinsic carrier mobility at a low VDD operation, an efficient SiGe channel passivation with low interface state densities (Dit) needs to be developped. However, the presence of GeO is known to increase Dit [1]. One of the effective passivation schemes for SiGe-based channel surface uses an epitaxially-grown ultrathin Si cap [2]. It suppresses the formation of GeO and enables to fabricate a high-k/SiO2 gate stack equivalent to the one in Si devices. The outstanding improvement achieved with this approach was previously highlighted on pure Ge channel devices, where the formation of GeO is inevitable without the use of Si-cap [3]. On the other hand, it poses some concerns such as EOT penalty and process controllability, making the Si-cap-free route the desired option as long as the interface and oxide bulk trap densities can be kept under control. In this contribution, we will review our recent studies towards the realization of a low-Dit Si-cap-free SiGe gate stack [4]. Selective GeO scavenging from Si1-xGexOy interface layer was previously reported as the key process to reduce Dit of SiGe gate stack [1]. Wostyn et al., demonstrated on Si0.75Ge0.25 that the annealing of chemical oxide in inert ambient (i.e. H2) reduces GeO in Si1-xGexOy IL thanks to the conversion of the thermally-unstable GeO into SiO [5]. A MOS capacitor experiment confirmed a clear Dit reduction by H2 anneal, although at an increased EOT. Additional NH3 anneal on IL was found to further reduce the Dit down to 5×1011 cm-2eV-1 while cancelling out the H2-anneal-induced EOT increase (EOT=10.1 Å). We also found that the metal gate deposition process has a strong impact on Dit even for the same metal. While the PVD W/TiN led to low Dit and EOT, both of them increased as the PVD was changed to ALD (or ALD followed by CVD) process. This can be explained by the PVD-TiN-induced additional GeO scavenging from IL [6] and/or oxygen diffusion from ALD-based metal to IL through HfO2 inducing GeO formation. A nitridation of HfO2 was found to suppress the negative impact from ALD-based metal electrode. XPS confirmed that the significant Dit reduction coincides with the nitridation of HfO2. By replacing the HfO2 with other dielectrics in which lower oxygen diffusivity is expected such as SiO2, the Dit of SiGe gate stack became insensitive to the metal deposition process and nitridation, indicating that the high oxygen diffusivity of the HfO2 layer was, together with the GeO formation, the root cause of the process-sensitive Dit. These results emphasize the importance of the oxygen depth profile control for the realization of a low-Dit SiGe gate stack.

On Mobility-Aware and Channel-Randomness-Adaptive Optimal Neighbor Discovery for Vehicular Networks

Neighbor information perception with high accuracy and low overhead is quite essential for vehicular networks, which is accomplished by the neighbor discovery scheme. Following the scheme, nodes exchange short discovery messages for advertising their existence and sensing neighboring vehicles. To combat high vehicle mobility and severe channel fading, the discovery message is always exchanged frequently in vehicular networks. This, however, introduces superabundant communication overhead. In this article, a novel neighbor discovery method with mobility awareness and channel randomness adaptability is proposed for investigating the aforementioned issue. First, a closed-form expression is derived, which captures the quantitive relation of the neighbor discovery performance to the vehicle mobility and channel randomness. Guided by our theoretical analysis, the optimal neighbor discovery scheme is developed to adjust the discovery frequency adaptively based on mobility and channel. Thus, an optimal tradeoff between the discovery accuracy and overhead is achieved in vehicular networks. Simulation results coincide with our analysis results, which further demonstrates that the proposed discovery scheme outperforms the periodic and existing adaptive methods in terms of discovery accuracy and overhead.