High Channel Doping Research Articles

Extracting edge conduction around threshold in mesa-isolated SOI MOSFETs

This work proposes a methodology to decompose the center and edge current contributions around threshold in mesa-isolated SOI MOSFETs using 3D TCAD simulations. Applied to pMOS measurements, it reveals that the subthreshold regime is driven by the active edge, whatever the device width. It also explains why the threshold voltage modulation by the back-gate bias depends on the device width, as well as why these effects are worse for high channel doping values.

SEU Performance Enhancement in BPJLT Devices by Channel Doping and Film Thickness

The bulk planar junctionless transistor (BPJLT) is a potential candidate for future CMOS technologies due to its CMOS compatibility and scalability. In this paper, the impact of silicon film thickness and channel doping on single-event upset (SEU) radiation performance of BPJLT based SRAMs is studied using TCAD simulations. The simulation results show that BPJLT devices having higher channel doping and smaller film thickness provides the better SEU performance.

Analog Figure-of-Merits Comparison of Gate Workfunction Variability and Random Discrete Dopant Between Inversion-Mode and Junctionless Nanowire FETs.

The analog figure-of-merits (FOMs) of conventional inversion-mode (IM) and junctionless (JL) NanoWire Field Effect Transistor (NWFET) have been investigated, considering the gate Work-Function Variability (WFV) and Random Discrete Dopant (RDD) using 3-dimensional (3D) TCAD simulation. While the JL-NWFET shows higher immune to WFV on analog FOMs, it can be easily affected by RDD due to higher channel doping level. On the other hand, the IM-NWFET shows stronger correlation between transconductance (gm) and gate capacitance (Cgg), leading to similar variation in cut-off frequency (ft) even though it shows larger gm and Cgg variation compared to JL-NWFET.

Two dimensional hole gas (2DHG) germanium junctionless P-FinFETs without impurity scattering achieved by modulation doping in channel

For the junctionless field-effect transistors (JL-FETs), there is a big concern that the high channel doping degrades carrier mobility by ionized impurity scattering mechanism. In this work, a sandwiched Ge/GeSi/Ge layer structure is proposed to be used as JL-FinFET channel, and only the middle GeSi layer is modulation doped by B atoms. In this structure, two dimensional hole gas (2DHG) forms in the top and bottom Ge channel layers, and is separated from B dopant impurity in the middle GeSi layer. Due to high hole mobility of 2DHG, the device exhibits an enhanced on-state current. The finished 2DHG Ge JL-FinFET shows a 6× current enhancement as compared to controlled Ge JL-FinFET with a uniformly B-doped Ge channel.

Behavior of subthreshold conduction in junctionless transistors

In this work, the effect of high channel doping concentration and unique structure of junctionless transistors (JLTs) is investigated in the subthreshold conduction regime. Both experimental results and simulation work show that JLTs have reduced portion of the diffusion conduction and lower effective barrier height between source/drain and the silicon channel in subthreshold regime, compared to conventional inversion-mode (IM) transistors. Finally, it leads to a relatively large DIBL value in JLTs, owing to degraded gate controllability on channel region and strong drain bias effect. However, JLTs showed a better immunity against short channel effect in terms of degradation of the effective barrier height value.

The study of relation between variable retention time and channel implantation

In this paper, we investigate a Random Telegraph Signal (RTS) like junction leakage current causing a variable retention time (VRT) problem in Dynamic Random Access Memory (DRAM) cells. With sample devices which have different channel doping concentration, hold times of high leakage state and low leakage state are extracted in diverse storage node bias conditions, and their ratios are analyzed based on a simple equation. The hold time ratio of two states decreases with the increasing bias in high channel doping samples, while it increases in both regular channel doping samples and low channel doping samples.

A 2-D analytical threshold-voltage model for GeOI/GeON MOSFET with high-k gate dielectric

A 2-D analytical threshold-voltage model for ultra-thin-body MOSFET with buried insulator and high-k gate dielectric is established by solving the 2-D Poisson's equation for the gate-dielectric, channel and buried-insulator regions. The validity of the model is confirmed by comparing with experimental data and other models. Using the model, the influences of gate-dielectric permittivity, buried-insulator permittivity, channel thickness, buried-insulator thickness and channel doping concentration on threshold behaviors are investigated. It is found that the threshold behaviors can be improved by using buried insulator with low permittivity, thin channel and high channel doping concentration. However, the threshold performance would be degraded when high-k gate dielectric is used due to enhanced fringing-field effect.

SEB Hardened Power MOSFETs With High-K Dielectrics

Simulations of the SEB hardness of power MOSFETs are carried out with an experimentally calibrated structure. The effects of incorporating high permittivity gate dielectric layers and increasing channel doping concentration are investigated. The simulation results indicate that high-k dielectrics and high channel doping are promising methods to achieve SEB-hardened power MOSFETs. This offers a potential path to power MOSFETs that are resistant to SEB with thinner, more radiation-tolerant gate dielectrics.

A Steep Subthreshold Swing Technique for Gate-All-Around SOI MOSFETs

A device design technique for nanowire FETs for low power capability beyond 10 nm technology node is proposed using 3D numerical simulation and physical analysis. The subthreshold kink effect enables the use of low supply bias without compromising performance. The proposed technique overcomes the fundamental and thermal voltage-limited subthreshold swing (SS). As end of technology roadmap is being approached, many solutions to extend Moore’s Law have been proposed. As the leakage current, mainly coming from the short-channel effects (SCEs), is becoming a limiting factor, the supply bias, i.e. VDD, has to decrease as the channel dimension continues to shrink. However, in order to provide a good CMOS logic, on-off current ratio, which is linked to SS, has to maintain at least three orders. Such limitation has prevented the supply bias from further scaling down. It would be a great deal if we can reduce SS. In SOI-based MOSFETs, floating body effects (FBEs) have addressed a concern for design, especially for a partially depleted body. Fully depleted SOI (Fig. 1) is considered a simpler device as FBEs are minimized. Among FBEs, the kink effect in subthreshold regime and in strong inversion due to impact ionization was once a big issue for the concern of raised off leakage current (Ioff). Nontheless, such concern has long gone since fully depleted SOI emerged. For the kink mechanism, the quasi neutral body in which the injected holes are stored is needed (Fig. 2), but it does not exist in fully depleted devices. Among nonplaner emerging transistors, gate-all-around (GAA) nanowire MOSFET shows superior SCE control due to excellent electrostatics. The GAA channel is usually design with a small diameter to meet the scale length requirement. FBEs are never of concern in the strongly depleted body. We found that using a proper scheme of channel doping, the subthreshold kink is observed. Furthermore, if the kink is away from VGS = 0 V, Ioff is not influenced. Using such technique, we were able to lower SS to less than 60 mV/dec. Fig. 3 shows the GAA n-MOSFET for simulation with gate length (L) of 5 nm, gate oxide thickness of 0.4 nm, channel doping of 1e19 cm^-3 and source/drain doping of 1e20 cm^-3 following ITRS. The high channel doping is intended to create a quasi neutral body for FBEs to effect. Such doping level is now a viable option as in-situ doping has become widely accepted. Fig. 4 shows IDS versus VGS characteristics, where the subthreshold kink at high drain bias is observed. Fig. 5 shows IDS versus VGS characteristics for different channel doping levels, indicating high doping is needed. Figs. 6 and 7 show hole density at different biases, respectively. As can be seen, holes are being accumulated when VGS is set to the condition for the kink to occur. A kink-assisted steep SS scheme was proposed for GAA MOSFETs using in-situ doping technique. Though additional channel doping induces impurity scattering and hence degrades drive current, the benefit from steep SS could overwhelm such drawback if designed properly when seeking for lower supply bias. Figure 1

Scaling junctionless multigate field-effect transistors by step-doping

Conventional junctionless (JL) multigate field-effect transistors (MuGFETs) use extremely scaled and highly doped fins as channels. Such small fins introduce large parasitic resistance as well as performance fluctuation due to fin width variations. The high channel doping significantly reduces bulk carrier mobility, which reduces on-state current and escalates short channel effect related leakage. In this letter, we present a step-doping scheme for the scaling of JL MuGFETs. By employing a two-step-doping profile, with the high doping side near the gate, higher threshold voltage and better off-state performance can be achieved, along with higher on-state current. This opens a route for threshold voltage design and addresses the design optimization for both on-state current and off-state leakage for JL MuGFETs.

RTN distribution comparison for bulk, FDSOI and FinFETs devices

In this paper we investigate the sensitivity of RTN noise spectra to statistical variability alone and in combination with variability in the traps properties, such as trap level and trap activation energy. By means of 3D statistical simulation, we demonstrate the latter to be mostly responsible for noise density spectra dispersion, due to its large impact on the RTN characteristic time. As a result FinFETs devices are shown to be slightly more sensitive to RTN than FDSOI devices. In comparison bulk MOSFETs are strongly disadvantaged by the statistical variability associated with high channel doping.

Variability Impact of Random Dopant Fluctuation on Nanoscale Junctionless FinFETs

Junctionless fin held-effect transistor (FinFET) variability due to random dopant fluctuation (RDF) was investigated for sub-32-nm technology generations using technology computer-aided design (TCAD) simulations. Results indicate that variations in threshold voltage, drive current, leakage current, and drain-induced barrier lowering are heavily impacted by RDF for junctionless FinFETs with sufficiently high channel doping (greater than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> ). Unexpectedly, the RDF impact is found to be less severe for finer technology generations, although the overall magnitude is still significant compared to line-edge-roughness-induced variability.

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain

In this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ⩾2.5GPa uniaxial tensile stress in the Si nanowire is reported. The deeply scaled Si nanowire including such uniaxial tensile stress shows a low-field electron mobility of 332cm2/Vs at room temperature, 32% higher than bulk mobility at the equivalent high channel doping. The conduction mechanism as well as high temperature performance was studied based on the electrical characteristics from room temperature up to ≈400K and a VTH drift of −1.72mV/K and an ionized impurity scattering-based mobility reduction were observed.

Behavior of triple-gate Bulk FinFETs with and without DTMOS operation

In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-planar structure is experimentally studied in triple-gate FinFETs. The drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DT mode and the standard biasing configuration. Moreover, for the first time, the important figures of merit for the analog performance such as transconductance-over-drain current, output conductance, Early voltage and intrinsic voltage gain will be studied experimentally and through three-dimensional (3-D) numerical simulations for different channel doping concentrations in triple-gate DTMOS FinFETs. The results indicate that the DTMOS FinFETs always yield superior characteristics and larger transistor efficiency. In addition, DTMOS devices with a high channel doping concentration exhibit much better analog performance compared to the normal operation mode, which is desirable for high performance low-power/low-voltage applications.

Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors

A bulk current model is formulated for long-channel double-gate junctionless (DGJL) transistors. Using a depletion approximation, an analytical expression is derived from the Poisson equation to find channel potential, which expresses the dependence of depletion width under an applied gate voltage. The depletion width equation is further simplified by the unique characteristic of junctionless transistors, i.e., a high channel doping concentration. From the depletion width formula, the bulk current model is constructed using Ohm's law. In addition, an analytical expression for subthreshold current is derived. The proposed model is compared with simulation data, revealing good agreement. The simplicity of the model gives a fast and easy way to understand, analyze, and design DGJL transistors comprehensively.

Optimization of SiC MESFET for High Power and High Frequency Applications

SiC MESFETs were scaled both laterally and vertically to optimize high frequency and high power performance. Two types of epi-stacks of SiC MESFETs were fabricated and measured. The first type has a doping of 3×1017 cm-3 in the channel and the second type has higher doping (5×1017 cm-3) in the channel. The higher doping allows the channel to be thinner for the same current density and therefore a reduction of the aspect ratio is possible. This could impede short channel effects. For the material with higher channel doping the maximum transconductance is 58 mS/mm. The maximum current gain frequency, fT, and maximum frequency of oscillation, fmax, is 9.8 GHz and 23.9 GHz, and 12.4 GHz and 28.2 GHz for the MESFET with lower doped channel and higher doping, respectively.

Quantum Confinement Induced Performance Enhancement in Sub-5-nm Lithographic Si Nanowire Transistors

We demonstrate lithographically fabricated Si nanowire field effect transistors (FETs) with long Si nanowires of tiny cross sectional size (∼3-5 nm) exhibiting high performance without employing complementarily doped junctions or high channel doping. These nanowire FETs show high peak hole mobility (as high as over 1200 cm(2)/(V s)), current density, and drive current as well as low drain leakage current and high on/off ratio. Comparison of nanowire FETs with nanobelt FETs shows enhanced performance is a result of significant quantum confinement in these 3-5 nm wires. This study suggests simple (no additional doping) FETs using tiny top-down nanowires can deliver high performance for potential impact on both CMOS scaling and emerging applications such as biosensing.

A Closed-Form Model for Position-Dependent Potential across the Channel in DG-MOSFETs

A closed-form model for electrostatic potential distribution in the direction normal to the channel for double-gate (DG) MOSFETs is presented. The effects of doping (NA for nMOS) and minority carriers both are taken into account for the first time, in solving Poisson's equation analytically. Excellent agreement between model-predicted results and numerical device simulation is achieved for a wide range of body thickness, light or high channel-doping, under various bias conditions. This complete closed form for position-dependent potential distribution has wide applications for MOS compact modelling and device design.

Corner effects in double-gate/gate-all-around MOSFETs

Two kinds of corner effects existing in double-gate (DG) and gate-all-around (GAA) MOSFETs have been investigated by three-dimensional (3D) and two-dimensional (2D) simulations. It is found that the corner effect caused by conterminous gates, which is usually deemed to deteriorate the transistor performance, does not always play a negative role in GAA transistors. It can suppress the leakage current of transistors with low channel doping, though it will enhance the leakage current at high channel doping. The study of another kind of corner effect, which exists in the corner at the bottom of the silicon pillar of DG/GAA vertical MOSFETs, indicates that the D-top structure with drain on the top of the device pillar of vertical transistor shows great advantage due to lower leakage current and better DIBL (drain induced barrier lowering) effect immunity than the S-top structure with source on the top of the device pillar. Therefore the D-top structure is more suitable when the requirement in leakage current and short channel character is critical.

A Physically Based Analytical Model for the Threshold Voltage of Strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.