High Aspect Ratio Through Silicon Via Research Articles

Electroless Plating of Diffusion Barrier Films on SiO2 and Evaluation of Film Characteristics

For fabrication of through-silicon via (TSV) of 3-D integration, sputtering or ALD are used for the barrier and seed layers formation, however, high cost processes using high vacuum instruments have hindered wide application of 3-D integration technologies. We have studied formation of barrier and seed layers with electroless plating which enables significant reduction of fabrication cost [1, 2]. Use of Pd nanoparticle catalyst adsorbed on silane coupling agent at TSV sidewall [3] is very effective for a highly conformal film deposition in the high aspect ratio TSV holes. In this study, we formed electroless barrier films such as CoWP and NiWP on SiO2 at various bath conditions. We evaluated film characteristics such as electrical resistivity, crystalline structure, adhesion property, alloy composition, Cu diffusion barrier properties, etc.Figure 1 shows SEM cross-sectional images of the barrier films and XRD profiles before and after annealing (400 oC, 30min. in vacuum).The crystalline structure of the as deposited CoWP film was amorphous and it remained almost amorphous after heat-treatment. On the other hand, the crystal structure of the as deposited NiWP film was also amorphous, but several peaks of NiP alloy appeared after heat-treatment and it turned to poly crystal film. In addition, we formed Cu seed layer on the barrier metal by displacement plating and studied Cu inter- diffusion properties after annealing. Reference [1] F. Inoue, T. Shimizu, H. Miyake, R. Arima,T. Ito, H.Seki,Y. Shinozaki, T. Yamamoto, and S.Shingubara, Microelectronic Engineering, 106(2013) 164–167. [2] F.Inoue, T.Shimizu, T. Yokoyama, H. Miyake, K. Kondo, T. Saito, T. Hayashi, S. Tanaka, T. Terui and S. Shingubara, Electrochimica Acta, 56-17 ,6245-6250, (2011). [3]W. J. Dressick, C. D. Dukey, J. H. Georger. Jr, G. S. Carabrese, and J. M. Calvert, J Electrochem. Soc., 141 (1) 210 (1994) Figure 1

Electrografted P4VP as Dielectric in High Aspect Ratio TSV: Surface Preparation and Thermomechanical Consideration

A challenge to most 3D integration approaches is the deposition of the Through-Silicon-Via (TSV) dielectric layer. A TSV is traditionally electrically insulated from the silicon substrate by a thin SiO2 film. As TSV aspect ratio gets higher, conformal SiO2 dielectric deposition becomes much more challenging. Alchimer has proposed as dielectric, the use of a highly conformal organic (poly-4-vinylpyridine, P4VP) as dielectric, electrografted through electrochemical reduction of diazonium salts in aqueous media. Surface cleaning prior to electrografting process is a challenge, especially in via last approach. Moreover, the thermomechanical behavior of P4VP coated TSVs remains unknown. This information is most relevant for the layout optimization of 3D integrated microsystems. We will discuss the TSV surface preparation challenge prior to the electrografting process and present the first measurements of the stress induced in the silicon substrate around TSV insulate by P4VP.

Electrografted P4VP as Dielectric in High Aspect Ratio TSV: Surface Preparation and Thermomechanical Consideration

A key to most 3D integration approaches is the deposition of the Through-Silicon-Via (TSV) dielectric layer. A TSV is traditionally electrically insulated from the silicon substrate by a thin SiO2 film. As TSV aspect ratio is getting higher, conformal SiO2 dielectric deposition is getting harder. Alchimer has proposed a high conformal organic (poly-4-vinylpyridine, P4VP) as dielectric. This polymer is electrografted through electrochemical reduction of diazonium salts in aquous media. Although the electrografting process is well described in the literature [1, 2], electrical and thermomechanical properties of such material grafted onto silicon structure remain incomplete. This information is mandatory in order to optimize 3D integrated processor’s layout. Since electrografting mechanism is initiated from the surface [2], P4VP material properties and kinetic growth can vary with the surface preparation of the TSV. Results obtained on TSVs, with various surface preparations, insulated by electrografted P4VP suggest that the polymer is not only a good dielectric, but could allow a reduction of the Keep Out Zone (KOZ) size for a higher integration density. Furthermore, as P4VP is a viscoelastic material, its Young’s modulus is temperature dependent and dramatically drops down above its glass transition temperature. Such a material is particularly interesting to reduce stress as it can act as a buffer stress layer.We will present the study of electrical and thermomechanical properties of the electrografted P4VP dielectric realized on high aspect ratio TSV. We will discuss the impact of TSV surface preparation on the electrografting process and on the material properties of the P4VP grafted layer. Results will be compared to more conventional approaches based on a silicon oxide insulator. Acknowledgement Université de Sherbrooke, Natural Sciences and Engeeniring Research Council of Canada (NSERC), Institut National de la Recherche Scientifique (INRS), Teledyne Dalsa and Alchimer are gratefully acknowledged for their help and their financial support. Figure 1

High-aspect ratio through-silicon vias for the integration of microfluidic cooling with 3D microsystems

Microfluidic cooling technology is a promising thermal solution for high-performance three-dimensional integrated circuits (3D ICs). However, the integration of microfluidic cooling into 3D ICs inevitably impacts tier-to-tier through-silicon vias (TSVs) by increasing their length and diameter (for a fixed aspect ratio). To address this challenge, this paper presents the fabrication of very high-aspect ratio (23:1) TSVs within a microfluidic pin-fin heat sink using two types of silicon etch masks. Void-free TSVs are electrically characterized using X-ray inspection and four-point resistance measurements.

A Study on the Seed Step-Coverage Enhancement Process (SSEP) of through Silicon Via (TSV) Using Electrophoretic Deposition (EPD) of Pd/PVP Colloids

The seed step-coverage enhancement process (SSEP) using Pd/PVP (Polyvinylpyrrolidone) colloids were investigated for the filling of through silicon via (TSV) without void. TEM analysis showed that the Pd nano-particles were well dispersed in aqueous colloidal solution with average diameter of 5.67 nm. These Pd nano-particles were uniformly deposited on the substrate of Si/SiO2/Ti wafer by electrophoresis with high frequency alternating current (AC). After electroless Cu deposition on the substrate treated with Pd/PVP colloids, the adhesive property between deposited Cu layer and substrate was evaluated. As a result of that, the Cu deposit showed superior adhesion property in comparison with that on treated substrate by the existing Pd ion catalyst. Finally, by implementing the SSEP using Pd/PVP colloids in TSV, we achieved 700% improvement of step coverage of Cu seed layer compared to PVD process, resulting in void-free fillng in high aspect ratio TSV.

Electrografted Copper Seed Layer for High Aspect Ratio TSVs Interposer Metallization

Nowadays, Through Silicon Vias (TSV) with High Aspect Ratio (HAR > 8:1) are seriously mandatory in the 3D Integrated Circuits in order to maintain semiconductor performance trends into new technological advances. Consequently, successful integration of HAR TSVs requires solving key challenges in terms of technical (layer continuity, step coverage, adhesion) and industrial (scale-up to 300mm diameter wafer) developments. In this paper, one proposes to discuss those questions by means of the integration of an electrografting (eG) seed layer on a high conformal, but low conductive MOCVD TiN copper diffusion barrier. On the one hand, one studies the impact of different electrochemical parameters on eG Seed layer properties. On the other one, the encountered difficulties are presented and solutions are proposed to integrate eG Seed layer at a large scale i.e. on a specific industrial 300mm diameter wafer plating chamber.

Optimization of innovative approaches to the shortening of filling times in 3D integrated through-silicon vias (TSVs)

The continuously decreasing size of integrated circuits is the driving force for the emergence of three-dimensional (3D) integration. The through-silicon via (TSV) is the heart of 3D IC/Si integrations, providing the shortest vertical interconnections, and it has a large number of significant advantages. In this paper, a new additive system specifically developed for high aspect ratio TSVs is introduced for TSV electroplating. A wafer is patterned using the deep reactive ion etching (DRIE) technique, and the seed layer is deposited using the physical vapor deposition (PVD) technique. Anode position optimization, a multi-step TSV filling process, additive concentration and plating current density optimization are conducted to enhance the filling efficiency while maintaining the void-free filling profile. The availability is verified by the wafer-segment plating of TSVs. The mechanism is investigated using linear sweep voltammetry (LSV), chronoamperometry, and a numerical simulation method.

The Limitation and Optimization of Bottom-Up Growth Mode in Through Silicon Via Electroplating

An analytical model is developed for the bottom-up growth mode observed in the electroplating of high aspect ratio through-silicon vias (TSVs). The effects of various factors, including the feature geometry, the suppression effect of the suppressive additives and the applied electric current, on the filling process are discussed. The process window for void-free filling and its narrowing down with the reduction of TSV footprint are demonstrated in simulation. The motivation to introduce ramping current in the electroplating of high aspect ratio TSVs is analyzed. Reduced plating time is demonstrated for stepwise ramping of the input current. Using the proposed analytical model, a simulation methodology for fast searching of the optimal plating conditions in multiple-step plating schemes is introduced.

Electrografted Copper Seed Layer for High Aspect Ratio TSVs Interposer Metallization

After many years of developments, 3D Integrated Circuits have emerged as a potential key enabler for maintaining semiconductor performance trends. Through Silicon Vias (TSVs) sit at the foundation of the 3D-IC revolution for extending semiconductor integration into a new phase. Integrated device manufacturers and fabless design houses need small, high-density, fine-pitch vias for improving signal integrity and Si real-estate savings, without possibility to wait for very thin wafer processing and handling technologies to become a mainstream. Deep TSVs with Aspect Ratio (AR) greater than 10:1 elegantly fulfill those requirements. But they cannot be manufactured with acceptable yield/cost using traditional dry processes for liner, barrier and seed deposition. Conventional dry techniques show basic shortcomings and impose high capital investments. Beyond that, physical limitations of directional dry techniques prevent the deposited layer from reaching good step coverage or even continuity inside the vias, which is required to perform void-free gap filling with electroplated copper.To overcome those limitations, alternative wet solutions based on electrografting (eG) and chemical grafting (cG) technologies were developed. These latter are two fundamental molecular engineering technologies, delivering high-quality films (continuous, adherent and uniform) for high aspect ratio (HAR) TSVs. This paper will focus on the integration of eG copper seed as a mature solution for TSVs with HAR, to overcome PVD Copper limitations in those dimensions.Electrografting is based on surface chemistry formulations and processes. It is applied to conductive and semi-conductive surfaces, and enables self-oriented growth of thin coatings of various materials, initiated by in-situ chemical reactions between specific precursor molecules and the surface. Contrary to electro-deposition which requires a potential supply throughout deposition to fuel the redox processes, electrografting is an electro-initiated process which requires a charged electrode only for the grafting step, but not for the thickening. As eG is mainly a cathodic process, it can generally be applied to various metallic and semiconducting surfaces without any concern over oxide formation. In a first approach, electrografting was used for polymer deposition on various conductive and semi conductive substrates. In this case, the grafting occurs via a direct electron transfer from the cathode to the electro-active monomers in solution (Figure 1). Mechanisms of radical polymerization show that polymer electrografting is an electro-induced grafting process followed by a purely chemical propagation step (polymerization). The first electro-induced step is crucial to form the chemical bond between the polymer and the surface. A specific organic precursor (B) is used both to form a first primer grafted layer and to initiate the polymerization of the vinyl monomer (A) in solution. The termination step of the polymerization leads to the grafting of macromolecular chains (-[A-A-A]n-B) onto the first primer grafted layer. Based on the polymer electrografting concept, formulation and processes have been developed to graft metal layers onto various type of conductive and semi-conductive surfaces. In opposite, for instance, to copper electrodeposition which has to be performed on conductive layer to avoid terminal effect induced by resistive copper diffusion barrier layers, copper electrografting technology can interestingly be achieved on highly resistive substrates.A bath containing specific organics and copper has previously been developed to deposit the Cu seed layer. It has been shown that electrografted copper seed can directly be applied to various dry-deposited diffusion barriers (Ta, TaN, Ti, TiN, TiW) without any adhesion promoter in between.This paper deals with the integration of eG Seed layer on a conformal MoCVD TiN copper diffusion barrier on 8:1 aspect ratio TSVs. First, detailed mechanism of the electrografting process will be discussed. Secondly, the influence of the electrical barrier resistivity (PVD TiN, Ni vs MoCVD TiN) on the plating properties into the via will be presented for both experiments done at coupon level and up scaled in an industrial 300mm diameter wafer reactor. Plating differences will be considered in term of growth initiation and step coverage for these two experimental configurations. Fine tuning of the process parameters at the 300mm scale will then be examined to achieve a conformal, uniform and adherent copper seed layer in order to successfully respond to the high AR copper filling challenge in the TSV applications. Finally, void-free filling, integration in a conventional 3D process flow and electrical characterizations on high aspect ratio TSV middle daisy chains are ongoing. As a perspective to decrease the cost of TSV metallization, the entire wet metallization process flow including isolation, copper diffusion barrier, copper seed and copper fill steps will be developed at the end of this paper.

Low Cost, Scalable and Selective Electrochemical TSV Fill Technology for 3D IC Interconnects

Physical and economical limitations for 2D scaling (so called “Moore’s Law”) prevents further increase of integration density to improve the performance of integrated circuits (IC). These challenges have stimulated the development of 3D through-silicon via (TSV) technology (so called “More than Moore”) in order to increase the speed and the bandwidth of the devices as well as to decrease the form factor and power consumption of integrated microsystems. However, the implementation of 3D TSV technology is limited by the high cost of 3D TSV fill (due to the use of expensive vapor deposition and chemical-mechanical processes) and its poor scalability (due to low conformality of physical and chemical vapor deposited films) to high TSV aspect ratios and smaller via sizes (to increase I/O). The objective of this investigation is to address the cost and scalability issues in order to enable cost-effective and reliable fill of high aspect ratio 3D TSVs. In this paper, we will review the low temperature and scalable process technology for 3D TSV fill employing the selective electrochemical through-via metal (Ni alloy/Cu or Co alloy/Cu) filling technology which is more economical because it will eliminate expensive chemical-mechanical polishing (CMP) process and replace expensive plasma-enhanced chemical vapor deposition (PE CVD) and physical vapor deposition (PVD) processes with low cost, lower temperature (<100 oC), more scalable (AR > 30:1) selective electrochemical process (LoCoSS process). LoCoSS process technology includes the following major electrochemical process steps: anodic oxidation to form isolation layer, selective electroless barrier deposition and selective electrochemical fill that can be implemented using one LoCoSS electrochemical processing tool instead of four POR processing tools utilizing different technologies – PE CVD isolation, PVD barrier/seed, Electrofill and CMP.The activation of thin continuous electroless barrier films (Ni or Co alloys) with high adhesion on the isolation surface (SiO2) is challenging. To overcome this technical risk, a novel nanoactivation process has been developed with the use of self-assembled monolayers [Si-(CH2)x-NH2-OH] and catalytic functionalized nanoparticles (Pd/Cu). To increase the adhesion of the deposited barrier films, the covalent bonding between substrate and the SAM binding layer has been engineered through the proper choice of the functional groups. Selective activation has been achieved through the mechanical removal of catalysts from the front surface (except inside the TSV’s) and the use of photosensitive TiO2/catalyst process. Besides, robust and defect-free fill of high aspect ratio TSV’s requires the development of electroless Cu superfill process with the use of suppressing additives in the plating solution such as high molecular weight polyacrylic acid (PAA) and polyethylene glycols (PEG). Selective electroless Cu plating into high aspect ratio TSV was successfully demonstrated with complete coverage of electroless barrier layer and low overplating on the field. Copper electroplating from NANO3D suppression-based plating solutions was also used to enable high speed and uniform plating of flat Cu bumps that can be used to interconnect chips in 3D microelectronics systems. LoCoSS technology could accelerate the mass-scale adoption of low cost and scalable TSV technology in semiconductor manufacturing. Implementation of our proprietary LoCoSS process will lower the cost of 3D ICs with the potential to reduce the cost by over 2X and increase scalability by over 3X for volume production. Besides, enabling low cost 3D ICs with our technology will allow heterogeneous system generation for next generation smart phones and other communication devices as well as increase of the bandwidth, memory capacity and decrease of the signal transmission delay within computing chips.

Void Detection in TSVs With X-Ray Image Multithreshold Segmentation and Artificial Neural Networks

Through-silicon via (TSV) is a vertical channel that passes through a chip to connect stacked dies in 3-D packaging. Void may be produced during the high aspect ratio TSV filling process with copper electroplating method. Therefore, void detection becomes an important aspect for high-quality TSV devices. In this paper, a rapid void detection method using a single 2-D X-ray imaging was developed. An image processing method was used to divide the X-ray image into some small blocks for multithreshold image cutting and feature extraction. An artificial neural network was then used to find and locate the blocks that contain voids. The effects of segmentation threshold, various block widths, and heights were studied; a block size of 30 × 40 pixels (width × height) is recommended. The void detection is more sensitive to block width than height. Experiments show that the method proposed in this paper can automatically and rapidly detect voids in TSVs using one 2-D X-ray image.

Pd/Cu/PVP 콜로이드를 이용한 고종횡비 실리콘 관통전극 내 구리씨앗층의 단차피복도 개선에 관한 연구

The seed step-coverage enhancement process (SSEP) using Pd/Cu/PVP colloids was investigated for the filling of through silicon via (TSV) without void. TEM analysis showed that the Pd/Cu nano-particles were well dispersed in aqueous solution with the average diameter of 6.18 nm. This Pd/Cu nano-particles were uniformly deposited on the substrate of Si/<TEX>$SiO_2$</TEX>/Ti wafer using electrophoresis with the high frequency Alternating Current (AC). After electroless Cu deposition on the substrate treated with Pd/Cu/PVP colloids, the adhesive property between deposited Cu layer and substrate was evaluated. The Cu deposit obtained by SSEP with Pd/Cu/PVP colloids showed superior adhesion property to that on Pd ion catalyst-treated substrate. Finally, by implementing the SSEP using Pd/Cu/PVP colloids, we achieved 700% improvement of step coverage of Cu seed layer compared to PVD process, resulting in void-free filling in high aspect ratio TSV.

Analysis of High Aspect Ratio through Silicon via (TSV) Diffusion and Stress Impact Profile during 3D Advanced Integration

In order to overcome the performances, dimensions and cost limit beyond the 22 nm technology node, three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective solution. Another potential of the TSVs is their promises in enabling advanced multi-level chips, integrating heterogeneous CMOS technologies with emerging technologies such as MEMS and bio-chips.As many integration schemes include the need of high aspect ratio TSVs in order to increase silicon thickness for Die bow and warp limitations or decrease TSV diameter for density increase, TSV Metallization, particularly barrier and seed layer deposition, has become a critical process step of the integration. In a previous work, the investigation of a low temperature (200°C) MOCVD TiN film as a barrier layer to prevent copper diffusion was studied. From these studies, it comes out that even a 5nm thin TiN film withstand barrier efficiency thermal test on fullsheet deposition. This barrier shows up a different behavior while being integrated in the high aspect ratio TSV due to subsequent plasma treatment during the deposition. Actually, the plasma densification does not have the same efficiency through the sidewall of the 80 µm deep TSV thereby enabling a different material structure all along the profile of the via. Characterizations of the behavior of the barrier in the TSV then become a great challenge in order to handle the integration protocol both in horizontal and vertical scales. Working at this scale of topology makes standard diffusion methods limited to evaluate the intrinsic diffusion properties into the via. A localized diffusion methods using Tof-SIMS along the sidewall of the TSV was used to overcome these geometrical issues (figure 1). This technique allowed us to compare different type of barriers and the determination of the minimal thickness for the efficiency of these films as a barrier in the TSV.3-D stacking using TSV involves mechanical and thermal stresses in the Cu TSV itself as well as in the surrounding silicon substrate. As the Cu volume of the TSV becomes important compared to the size of the active components, stresses are induced extrinsically by the interaction of every metallurgical step of the TSV elaboration, including dielectric isolation, barrier/seed layer and copper filling depositions as well as subsequent copper anneals. Stresses can be induced intrinsically by thermal treatment due to the mismatch of thermal expansion between the via material and Si. Usually the X-rays diffraction (XRD) and the stress distribution from the variation of the curvature during the processing is used to measure the stress induced in thin films. Due to the depth of the structure, these methods are limited to measure the stress generated by the TSV.Micro Raman spectroscopy measurements allow measuring the stress induced by every single metallurgical step of the TSV elaboration. For the barrier layer step, the intrinsic stress generated into the silicon by different types of TiN barrier according to process parameters and subsequent plasma treatment were measured and compared (Figure 2). It comes out that some barriers induced a more compressive stress in the silicon and others seem to have a tensile behavior. Then the evolution of the stress of the TSV through different anneal conditions were studied to evaluate the stability of the via with the temperature.

(Invited) Metrology for 3D Integration

Three-dimensional stacked integrated circuits (3DS-IC) fabrication requires complex technologies such as high-aspect ratio through-silicon vias (TSVs), wafer thinning, thin wafer handling and processing, and bonding of thin wafers with complex patterned surfaces. The implementation 3DS-IC also presents significant metrology challenges. This talk will give an overview of the metrology needs for 3DS-IC, identify solutions, and describe work towards the development of standards to support the 3D ecosystem. One of these standards under development is investigating methods for identifying and characterizing voids between bonded wafers. Wafer bonding in a 3DS-IC process is typically an intermediate step. After bonding, one or both of the wafers will undergo processes such as thinning, thin film deposition, lithography, and patterning. The presence of voids between the wafers will cause significant stack thickness variation, which can lead to failure at one or more of these steps. A number of tools can be used to identify and/or characterize voids; this standard will provide members of the 3DS-IC community with guidance for choosing the tool or tools that will best address the specific need. Preliminary results from a round robin experiment, involving approximately 20 laboratories, will be shown. This experiment uses as a test structure a bonded wafer pair with a number of voids patterned into one of the wafers before bonding. The sizes of the programmed voids range from 0.5 μm to 300 μm with depths of 15 nm to 1200 nm and are placed in isolated, semi-dense, and dense patterns. A scanning acoustic microscope image of one instance of the test chip with patterned voids is shown in the figure.

(Invited) Metrology for 3D Integration

Three-dimensional stacked integrated circuit (3DS-IC) fabrication requires complex technologies such as high-aspect ratio through-silicon vias (TSVs), wafer thinning, thin wafer handling and processing, and bonding of thin wafers with complex patterned surfaces. Each of these new fabrication steps is associated with metrology challenges. The SEMI 3DS-IC Committee is developing a set of guides to assist the 3DS-IC community in addressing these challenges by identifying metrology solutions. In this paper we provide an overview of the metrology needs for 3DS-IC, identify metrology solutions, and provide examples from SEMI standards describing methods for characterizing the quality and strength of bonds between wafers.

Si Etching for TSV Formation

Through silicon via (TSV) technology is being considered as a promising technology in three-dimensional packaging, enabling massive and short interconnections between stacked chips, increasing performance and data bandwidth, and reducing signal delay and the power consumption. Currently, TSVs with diameters ranging from one hundred to ten micrometers are mainly fabricated by deep reactive ion etching (DRIE) technology. The Bosch process is the most widely utilized DRIE process for producing high-aspect ratio TSVs. The primary steps in the Bosch process are silicon isotropic etching and wall passivation in sequential cycles. SF6 is used as the main etching gas for the high density of F+ radicals; C4F8 is used in wall passivation as it polymerizes to deposits on walls to form an etch barrier that is sufficiently impervious to side scattered F+ ions but not to direct ions at the bottom of the via. Wall scalloping occurs primarily near the top of the via where scattered ions have wide trajectories and less at greater depths where ion trajectories are more restricted. Controlling the scallop is key good insulation and metal coverage. In this study, TSVs with scallops smaller than 100nm was obtained by adjusting the flow ratio of SF6 to C4F8 and the cycle time ratio between SF6 and C4F8. Unfortunately this combination leads to the formation of silicon grass at the bottom of the TSV. The addition of O2 during the SF6 etch cycle was found to eliminate the occurrence of Si grass. Finally, TSVs with low scallop were consistently obtained without Si grass by using SF6/O2 during the etch cycle and C4F8 during the passivation cycle.

Fully back-end TSV process by Cu electro-less plating for 3D smart sensor systems

A fully back-end process for high-aspect ratio through-silicon vias (TSVs) for 3D smart sensor systems is developed. Atomic layer deposition of TiN provides a highly conformal barrier as well as a seed layer for metal plating. Cu electro-less plating on the chemically activated TiN surfaces is applied to uniformly fill the TSVs in a significantly shorter time (2 h for 300 μm deep and 20 μm wide TSVs) than with Cu bottom-up electroplating (>20 h). The process is CMOS compatible and can be performed after the last metalization step, making it a fully back-end process (VIA-last approach). Wafers containing metal interconnections on both sides are in fact used as demonstrator. Four-terminal 3D Kelvin structures are fabricated and characterized. An average resistance value of 650 mΩ is measured for 300 μm deep TSVs with an aspect ratio of 15. The crosstalk between adjacent TSVs is also measured by means of S-parameters characterization on dedicated RF test structures. The closest TSVs (75 μm) show a reciprocal crosstalk of less than −20 dB at 30 GHz.

High aspect ratio and low capacitance through-silicon-vias (TSVs) with polymer insulation layers

► TSVs using poly (propylene carbonate) (PPC) polymer as insulators have been developed. ► The TSV capacitance density is as low as 2.45 nF/cm 2 , about one tenth of TSVs using SiO 2 insulators. ► The leakage current at 5 V biased voltage is as low as 40 nA/cm 2 . Polymer insulation layers (liners) have several potential advantages in terms of capacitance and reliability over conventional silicon dioxide for through-silicon-via (TSV) applications. This paper reports the development and measurement results of a TSV using poly (propylene carbonate) (PPC) polymer as the insulation layers. To address the challenge in coating thin and uniform PPC liners on the sidewalls of high aspect-ratio vias, a spin-on technique using vacuum treatment and solvent refill is developed to prevent formation of air bubbles in the vias, and using this technique circular vias with aspect-ratio as high as 9:1 have been coated with uniform PPC layers. Based on these results, TSVs with thick PPC polymer liners have been fabricated and the capacitance and the current leakage are measured. Thanks to the relatively large thickness and the low dielectric constant of PPC liners, the TSV capacitance density is about 2.45 nF/cm 2 and the leakage current is around 40 nA/cm 2 at 5 V voltage, indicating that replacing silicon dioxide with PPC as liners considerably reduces TSV capacitance. The preliminary results demonstrate the feasibility of fabrication of high aspect ratio and low capacitance TSVs with polymer liners.

Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires

Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect ratios (>20). Nickel wires are placed in via holes of a silicon wafer by an automated magnetic assembly process and are used as a conductive path of the TSV. This metal filling technique enables the reliable fabrication of through-wafer vias with very high aspect ratios and potentially eliminates characteristic cost drivers in the TSV production such as advanced metallization processes, wafer thinning and general issues associated with thin-wafer handling.

Benzocyclobutene polymer filling of high aspect-ratio annular trenches for fabrication of Through-Silicon-Vias (TSVs)

Through-Silicon-Vias (TSVs) with polymer liners have potential improved electrical and mechanical reliability for three-dimensional (3D) packaging/integration applications. To address the challenge in fabrication of polymer liners in high aspect-ratio TSVs, we have developed a vacuum-assisted spin-coating technology for filling benzocyclobutene (BCB) polymer in high aspect-ratio annular trenches. The newly developed spin-coating technology employs spin-coating twice and vacuum treatment after each coating. The vacuum treatment removes the bubbles at the trench bottom trapped during spin-coating and curing, and facilities the formation of void-free BCB filling. The influences of the BCB viscosities and the spin-coating parameters on the filling ability are evaluated, and upon optimization annular trenches with aspect-ratio as high as 22 have been successfully filled with no void formation, thin overburden, and slight dishing. This method is also applicable to trench filling using polymers with similar properties.