Abstract

A challenge to most 3D integration approaches is the deposition of the Through-Silicon-Via (TSV) dielectric layer. A TSV is traditionally electrically insulated from the silicon substrate by a thin SiO2 film. As TSV aspect ratio gets higher, conformal SiO2 dielectric deposition becomes much more challenging. Alchimer has proposed as dielectric, the use of a highly conformal organic (poly-4-vinylpyridine, P4VP) as dielectric, electrografted through electrochemical reduction of diazonium salts in aqueous media. Surface cleaning prior to electrografting process is a challenge, especially in via last approach. Moreover, the thermomechanical behavior of P4VP coated TSVs remains unknown. This information is most relevant for the layout optimization of 3D integrated microsystems. We will discuss the TSV surface preparation challenge prior to the electrografting process and present the first measurements of the stress induced in the silicon substrate around TSV insulate by P4VP.

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