Abstract

For fabrication of through-silicon via (TSV) of 3-D integration, sputtering or ALD are used for the barrier and seed layers formation, however, high cost processes using high vacuum instruments have hindered wide application of 3-D integration technologies. We have studied formation of barrier and seed layers with electroless plating which enables significant reduction of fabrication cost [1, 2]. Use of Pd nanoparticle catalyst adsorbed on silane coupling agent at TSV sidewall [3] is very effective for a highly conformal film deposition in the high aspect ratio TSV holes. In this study, we formed electroless barrier films such as CoWP and NiWP on SiO2 at various bath conditions. We evaluated film characteristics such as electrical resistivity, crystalline structure, adhesion property, alloy composition, Cu diffusion barrier properties, etc.Figure 1 shows SEM cross-sectional images of the barrier films and XRD profiles before and after annealing (400 oC, 30min. in vacuum).The crystalline structure of the as deposited CoWP film was amorphous and it remained almost amorphous after heat-treatment. On the other hand, the crystal structure of the as deposited NiWP film was also amorphous, but several peaks of NiP alloy appeared after heat-treatment and it turned to poly crystal film. In addition, we formed Cu seed layer on the barrier metal by displacement plating and studied Cu inter- diffusion properties after annealing. Reference [1] F. Inoue, T. Shimizu, H. Miyake, R. Arima,T. Ito, H.Seki,Y. Shinozaki, T. Yamamoto, and S.Shingubara, Microelectronic Engineering, 106(2013) 164–167. [2] F.Inoue, T.Shimizu, T. Yokoyama, H. Miyake, K. Kondo, T. Saito, T. Hayashi, S. Tanaka, T. Terui and S. Shingubara, Electrochimica Acta, 56-17 ,6245-6250, (2011). [3]W. J. Dressick, C. D. Dukey, J. H. Georger. Jr, G. S. Carabrese, and J. M. Calvert, J Electrochem. Soc., 141 (1) 210 (1994) Figure 1

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