Hardware Redundancy Techniques Research Articles

Fault Detection in Aircraft Flight Control Actuators Using Support Vector Machines

Future generations of flight control systems, such as those for unmanned autonomous vehicles (UAVs), are likely to be more adaptive and intelligent to cope with the extra safety and reliability requirements due to pilotless operations. An efficient fault detection and isolation (FDI) system is paramount and should be capable of monitoring the health status of an aircraft. Historically, hardware redundancy techniques have been used to detect faults. However, duplicating the actuators in an UAV is not ideal due to the high cost and large mass of additional components. Fortunately, aircraft actuator faults can also be detected using analytical redundancy techniques. In this study, a data-driven algorithm using Support Vector Machine (SVM) is designed. The aircraft actuator fault investigated is the loss-of-effectiveness (LOE) fault. The aim of the fault detection algorithm is to classify the feature vector data into a nominal or faulty class based on the health of the actuator. The results show that the SVM algorithm detects the LOE fault almost instantly, with an average accuracy of 99%.

Survey of Software-Implemented Soft Error Protection

As soft errors are important design concerns in embedded systems, several schemes have been presented to protect embedded systems against them. Embedded systems can be protected by hardware redundancy; however, hardware-based protections cannot provide flexible protection due to hardware-only protection modifications. Further, they incur significant overheads in terms of area, performance, and power consumption. Therefore, hardware redundancy techniques are not appropriate for resource-constrained embedded systems. On the other hand, software-based protection techniques can be an attractive alternative to protect embedded systems, especially specific-purpose architectures. This manuscript categorizes and compares software-based redundancy techniques for general-purpose and specific-purpose processors, such as VLIW (Very Long Instruction Word) and CGRA (Coarse-Grained Reconfigurable Architectures).

XOR Multiplexing Technique for Nanocomputers

In emerging nanotechnologies, due to the manufacturing process, a significant percentage of components may be faulty. In order to make systems based on unreliable nano-scale components reliable, it is necessary to design fault-tolerant architectures. This paper presents a novel fault-tolerant technique for nanocomputers, namely the XOR multiplexing technique. This hardware redundancy technique is based on a numerous duplication of faulty components. We analyze the error distributions of the XOR multiplexing unit and the error distributions of multiple stages of the XOR multiplexing system, then compare them to the NAND multiplexing unit and the NAND multiplexing multiple stages system, respectively. The simulation results show that XOR multiplexing is more reliable than NAND multiplexing. Bifurcation theory is used to analyze the fault-tolerant ability of the system and the results show that XOR multiplexing technique has a high fault-tolerant ability. Similarly to the NAND multiplexing technique, this fault-tolerant technique is a potentially effective fault tolerant technique for future nanoelectronics.

Single event transient sensitivity analysis of different 32 nm CMOS majority voters designs

As a consequence of the technology scaling, the reduced amount of energy needed to store information impacts the Linear Energy Transfer Threshold (LETth), implying in circuits more sensitive to radiation faults. Hardware redundancy techniques such as the Triple Modular Redundancy are constantly used to mitigate this problem. However, the weakness of the redundancy technique is the voter circuit, and for this reason, alternative designs have been proposed in the literature to improve the robustness of this block. This work investigates the robustness of different majority voter topologies in the presence of Single Event Transient (SET). A layout-level analysis using stick diagrams is fulfilled to analyze the impact a SET causes in diffusion areas shared by transistors, and a fault masking ratio is used to measure the voter robustness. Then an electrical-level analysis was done based on the information provided from the previous study to investigate the threshold LET. The results obtained in this study shown that the topologies can endure a LET up to 1.86 MeV·cm−2/mg considering the 32 nm CMOS technology.

Reliability prediction of on-board subsystem satellite by Monte Carlo methodology

This paper presents a case study that aims to develop a hardware design for the pc to the satellite, supported fault-tree design and calculations of dependableness. The on-board pc of a satellite, inserted into the on-board management system, has functions of receiving, process and distribution of commands to the subsystems and payload of the satellite; and exploit, formatting, storage and transmission of measurement from subsystems and payload. The most necessities of associate on-board pc are high dependableness, capability of real time process, resistance to radiation, and minimizing power consumption, volume and mass. Enlarged dependableness is achieved by the fault tolerance technique that relies on adding redundancy to the system, or the utilization of elements with high price of individual dependableness. During this work, hardware redundancy techniques are thought-about. First, a pc is meant and its dependableness is calculated, for a mission of one year period. Mission dependableness goal isn’t earned during this calculation. So as to extend dependableness, two kinds of fault tolerant redundant architectures are analyzed, with their various reliabilities calculated for the identical amount of the mission.

Kernelized technique for outliers detection to monitoring water pipeline based on WSNs

Currently, the technology for sensing and control has become the potential for significant advances not only in science and business but equally important on a range of industrial applications. In addition to reducing costs and increasing efficiencies for monitoring systems, Wireless Sensor Networking (WSN) is expected to bring consumers a new generation of conveniences. However, there are issues when treating extremely interrelated, composite, and noisy databases with a large dimension. For that purpose, outliers detection techniques (ODT) are used for an effective monitoring system to ensure the safety of a transport process. Therefore, in this paper, a novel model of outliers detection and classification has been developed to complement the existing hardware redundancy and limit checking techniques. To overcome these problems, we present a Combined Kernelized Outliers Detection Technique (CKODT) based WSN for damages detection in water pipeline. Initially, training pressure measurement is collected from the sensors which are implemented outside the pipe. Next, these data are fed into the data reduction algorithm as known as Kernel Fisher Discriminant Analysis (KFDA) to create discriminant vectors. Then, these vectors were utilized as inputs for the One Class Support Vector Machine (OCSVM) method to classify the feature sets which were extracted using the proposed technique. The main objective of this work was to combine the advantages of these tools to enhance the performance of the monitoring water pipeline system. The accuracy of our Combined Kernelized Outliers Detection Technique for classification was analyzed and compared with variety of techniques. The experimental results showed the improvements of the proposed framework compared to other techniques in the context of damage detection in the monitoring water pipeline process.

Kernel approaches for fault detection and classification in PARR-2

Safety and reliability of nuclear power plants is of utmost importance. For that purpose, modern fault detection and classification (FDC) techniques are being devised to compliment the existing hardware redundancy and limit checking techniques. Among these modern techniques, Fisher discriminant analysis (FDA) and support vector machines (SVM) have been shown to be successful for FDC of nuclear reactors. By considering the fact that both FDA and SVM are basically established for linear systems and nuclear reactors are highly nonlinear processes, it becomes more intuitive to utilize some nonlinear FDC technique. To this end, application of kernel based non-linear approaches including kernel FDA (KFDA) and kernel SVM (KSVM) is proposed in this paper for fault detection and classification in Pakistan Research Reactor-2. Control rod withdrawal and accidental external reactivity insertion faults are manually executed at PARR-2, and training data is collected from the reactor based on which KFDA and KSVM models are developed. The online data is subsequently tested using the developed models which resulted into reliable fault classification.

Detecting Dementia-Related Wandering Locomotion of Elders by Leveraging Active Infrared Sensors

For elders with dementia, wandering is among the most problematic, frequent and dangerous behavior. Managing wandering behavior has become increasingly imperative due to its high prevalence, negative outcomes and burden on caregivers. We study to propose an active infrared-based method to identify wandering locomotion by monitoring rhythmical repetition of an elder’s indoor motion events. Specifically, we utilize our customized active infrared sensors to collect human indoor motions that will be converted into motion events by using hardware redundancy technique. Each motion event is a directed motion obtained via introducing temporal and dimensions into the spatial motion data. Based on the most cited spatial-temporal patterns of wandering locomotion, a spatiotemporal model is then proposed to identify wandering locomotion from an ongoing sequence of motion events. Experimental evaluation on eight individuals’ real-world motion datasets has shown that our proposed method is able to effectively identify wandering locomotion from repetitive events collected from active infrared sensors with a value over 98% for both accuracy and precision based on properly chosen parameters. Wandering in elders with dementia that follow specific spatiotemporal patterns can be reliably identified by analyzing repetitive motion events collected from active infrared sensors based on the well-known spatiotemporal patterns of wandering locomotion.

A Flexible Fault Injection Platform for the Analysis of the Symptoms of Soft Errors in FPGA Soft Processors

Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in the FPGA configuration memory. To this end, we present a flexible fault injection platform based on an open-source CAD framework (RapidSmith) for the soft error sensitivity analysis of soft processors in Xilinx SRAM-based FPGAs. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. The fault injection is performed on-chip by a dedicated microcontroller which also monitors processor behavior to identify specific symptoms as consequences of soft errors. The performed analysis showed that these symptoms can be used to build an efficient, low-cost error detection scheme. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor.

FPGA implementation of area-efficient single precision floating point complex divider with fault detection

Despite the applications of complex division in many fields like signal processing, control theory, telecommunication, etc., complex division algorithms are often treated with least importance. Most of the complex division modules are to be used in environments where fault-tolerance is required. FPGA is considered as a major candidate to implement such computationally intensive tasks because of its inherent properties. Interconnect faults and logic faults are two of the major types of faults likely to occur in FPGAs. Most of the existing works on fault-tolerant complex division uses hardware redundancy technique. This work proposes a technique to implement a complex division module with fault detection capability on FPGA. A module reuse technique is used to make the architecture area-efficient. The operands are being represented in 32-bit single precision floating point format.

Built-In Self Test and Self-Repairing Circuit for Array Multipliers

Background/Objectives: As the size of the chip reduces, nanoscale devices have become more susceptible to manufacturing faults, interference from radiations and transient faults. Many of these errors are not permanent but it causes malfunctioning of circuit either due to the complexity of the circuit or due to the interaction with the software. In this paper, an area and power efficient BIST with self repairing technique has been proposed, which detect and repair the faults in the circuit. Methods/Statistical Analysis: In this research work, a novel Built-In Self-Test (BIST) architecture with self repairing circuit is proposed. The novelty of this architecture is that testing is done along with the self repairing. The Self repairing circuit repairs the fault in the circuit during testing phase itself which increases the reliability of the circuit. Since the insertion of test pattern externally, BIST architecture does not alter the basic multiplier structure. Findings: Average power dissipation of the proposed Built-in self test and self repairing of array multiplier architecture is reduced by 36% since the use of a power efficient test pattern generator. Self repairing has been accomplished by the use of hardware redundancy technique. Also a TMR based self repairing architecture for real time self repairing has been proposed and its area and power dissipation is compared with the other self repairing architecture. Result shows that the BIST with repairing technique is good for low power applications while the TMR based self repairing method is good for real time self repairing applications. The proposed technique can be extended to self repairing processor.

The study of hardware redundancy techniques to provide a fault tolerant system

Increasing the reliability of computer systems operations is feasible by means of fault tolerance. This tolerance in a digital system is achieved through redundancy in hardware, software, or computation. This sort of redundancy can be performed in static, dynamic, or hybrid configuration. Hardware redundancy is obtained by providing two or more physical samples of a hardware component. In this paper, we study different hardware redundancy techniques.Its efficiency and problems.

Low-Energy Standby-Sparing for Hard Real-Time Systems

Time-redundancy techniques are commonly used in real-time systems to achieve fault tolerance without incurring high energy overhead. However, reliability requirements of hard real-time systems that are used in safety-critical applications are so stringent that time-redundancy techniques are sometimes unable to achieve them. Standby sparing as a hardware-redundancy technique can be used to meet high reliability requirements of safety-critical applications. However, conventional standby-sparing techniques are not suitable for low-energy hard real-time systems as they either impose considerable energy overheads or are not proper for hard timing constraints. In this paper we provide a technique to use standby sparing for hard real-time systems with limited energy budgets. The principal contribution of this paper is an online energy-management technique which is specifically developed for standby-sparing systems that are used in hard real-time applications. This technique operates at runtime and exploits dynamic slacks to reduce the energy consumption while guaranteeing hard deadlines. We compared the low-energy standby-sparing (LESS) system with a low-energy time-redundancy system (from a previous work). The results show that for relaxed time constraints, the LESS system is more reliable and provides about 26% energy saving as compared to the time-redundancy system. For tight deadlines when the time-redundancy system is not sufficiently reliable (for safety-critical application), the LESS system preserves its reliability but with about 49% more energy consumption.

REDUNDANCY ISSUES IN SOFTWARE AND HARDWARE SYSTEMS: AN OVERVIEW

The redundancy is a widely spread technology of building computing systems that continue to operate satisfactorily in the presence of faults occurring in hardware and software components. The principle objective of applying redundancy is achieve reliability goals subject to techno-economic constraints. Due to a plenty of applications arising virtually in both industrial and military organizations especially in embedded fault tolerance systems including telecommunication, distributed computer systems, automated manufacturing systems, etc., the reliability and its dependability measures of redundant computer-based systems have become attractive features for the systems designers and production engineers. However, even with the best design of redundant computer-based systems, software and hardware failures may still occur due to many failure mechanisms leading to serious consequences such as huge economic losses, risk to human life, etc. The objective of present survey article is to discuss various key aspects, failure consequences, methodologies of redundant systems along with software and hardware redundancy techniques which have been developed at the reliability engineering level. The methodological aspects which depict the required steps to build a block diagram composed of components in different configurations as well as Markov and non-Markov state transition diagram representing the structural system has been elaborated. Furthermore, we describe the reliability of a specific redundant system and its comparison with a non redundant system to demonstrate the tractability of proposed models and its performance analysis.

Relevant metrics for evaluation of concurrent error detection schemes

Concurrent error detection (CED) schemes are becoming essential features in the design process as IC technologies progress into the nanoscale era. Soft error rate reduction has emerged as an important challenge and several works are dedicated to quantify the CED effective enhancement in systems reliability. However, none of them make a comprehensive description of the output events that can occur in such schemes. In this paper we propose a methodology to evaluate circuits with CED, including the time penalty as a relevant metric even in hardware redundancy techniques. Our experiments have shown that systems can reduce their throughput by half in multiple fault environments making the choice of the CED scheme strongly dependent on this analysis.

Software and Hardware Techniques for SEU Detection in IP Processors

In the recent years both software and hardware techniques have been adopted to carry out reliable designs, aimed at autonomously detecting the occurrence of faults, to allow discarding erroneous data and possibly performing the recovery of the system. The aim of this paper is the introduction of a combined use of software and hardware approaches to achieve a complete fault coverage in generic IP processors, with respect to SEU faults. Software techniques are preferably adopted to reduce the necessity and costs of modifying the processor architecture; since a complete fault coverage cannot be achieved, partial hardware redundancy techniques are then introduced to deal with the remaining, not covered, faults. The paper presents the methodological approach adopted to achieve the complete fault coverage, the proposed resulting architecture, and the experimental results gathered from the analysis of the fault injection campaigns.

An efficient fault-tolerant approach for mobile ip in wireless systems

This paper presents the fault tolerance of Mobile IP in wireless systems. Mobile IP can support wireless users with continuous network connections while changing locations. It is achieved by allocating a number of mobility agents (foreign agents and home agents) in the architecture of a wireless system. If a failure occurs in a mobility agent, the wireless users located in the coverage area of the faulty mobility agent will lose their network connections. To tolerate the failures of mobility agents, this paper proposes an efficient approach to maintaining the network connections of wireless users without being affected by the failures. Once detecting a failure in a mobility agent, failure-free mobility agents are dynamically selected to be organized as a backup set to take over the faulty mobility agent. Compared to the previous approaches, the proposed approach does not take any actions against failures during the failure-free period. Besides, the hardware redundancy technique is also not used in the proposed approach. The overhead of the proposed approach is analyzed using the M/G/c/c queuing model. The results show that the proposed approach can effectively resolve the fault-tolerant problem of Mobile IP in wireless systems.

Design of a complete multi-microcontroller based protection system for large diesel turbine generator

This paper presents a multi-microcontroller based protection system, which includes three relaying modules and one master control module, to realize parallel processing and background management. The proposed protection system is suitable to be employed as the primary and backup protection for a large diesel turbine generator. Hardware and software redundancy techniques are used, and the bottleneck effects of the single processor system are eliminated. The hardware of the protection system is modularized with the same architecture with respect to relaying modules. The master control module is responsible for system monitoring, communications and man-machine interfacing, it can reassign the protection functions in case of one relaying module failure.

An on-line expert system-based fault-tolerant control system

Fault-tolerant control systems have been studied very actively during recent years. Software and hardware redundancy techniques are the most common methods used to solve the problems. In recent years, expert systems or artificial intelligence have been used successfully in fault diagnosis of the dynamic systems and their suitability for fault-tolerant control problems has also been demonstrated. In this paper an on-tine expert system-based fault-tolerant control system (ESFTC) is considered which allows reconfiguration of the controller in feedback process systems during sensor or actuator failures or misoperudon. It forms an on-line expert system, which consists of an analytical problem solution, a process knowledge base, a knowledge acquisition part and an inference mechanism. The analytical problem solution is based on process coefficient changes, which are symptoms of process faults. A controller is reconfigured based on the symptoms. The process knowledge base comprises analytical knowledge in the form of process performances and heuristic knowledge in the form of fault trees and fault statistics. In the phase of knowledge acquisition the process specific knowledge, like theoretical process models, the abnormal behavior, failures and misoperation, is compiled The inference mechanism performs the fault-tolerant controller, based on the observable symptoms, controller trees, fault probabilities and process history. Case study experiments with the Yeast Fermentation Process Control System show the performance of the fault-tolerant controller.

Long-haul undersea communications systems: hardware redundancy techniques for ultra-reliability : Robert H. Murphy. Proc. A. Reliab. Maintainab. Symp., 164 (1990)

Long-haul undersea communications systems: hardware redundancy techniques for ultra-reliability : Robert H. Murphy. Proc. A. Reliab. Maintainab. Symp., 164 (1990)