Survey of Software-Implemented Soft Error Protection

Yohan Ko

doi:10.3390/electronics11030456

Abstract

As soft errors are important design concerns in embedded systems, several schemes have been presented to protect embedded systems against them. Embedded systems can be protected by hardware redundancy; however, hardware-based protections cannot provide flexible protection due to hardware-only protection modifications. Further, they incur significant overheads in terms of area, performance, and power consumption. Therefore, hardware redundancy techniques are not appropriate for resource-constrained embedded systems. On the other hand, software-based protection techniques can be an attractive alternative to protect embedded systems, especially specific-purpose architectures. This manuscript categorizes and compares software-based redundancy techniques for general-purpose and specific-purpose processors, such as VLIW (Very Long Instruction Word) and CGRA (Coarse-Grained Reconfigurable Architectures).

Highlights

IntroductionThe embedded processors’ reliability against soft errors is becoming a critical design concern, especially in embedded systems [1]
With technology scaling, the embedded processors’ reliability against soft errors is becoming a critical design concern, especially in embedded systems [1]
The reliability of embedded systems is becoming more critical as embedded systems could be exploited in crucial and safety-critical applications, such as fiscal programs, mobile healthcare devices, and automotive systems, in the near future [5]

Summary

Introduction

The embedded processors’ reliability against soft errors is becoming a critical design concern, especially in embedded systems [1]. The early stage of software-based duplication and checking techniques, such as EDDI, CFCSS, and SWIFT, can only detect transient faults These in-thread instruction replication sachems incur massive overheads in terms of performance and power consumption even with several optimization schemes [19,20]. Software-based redundant multi-threading schemes [23,24,25] have been presented in order to mitigate the performance overheads from purely software-implemented protections They execute the same operations on the leading and trailing threads and detect erroneous data by comparing results. In order to overcome the limitations of software-only approaches, techniques for minimal hardware modification with software protection have been presented They can perform complex design space exploration in terms of hardware area, costs, performance, power consumption, and reliability depending on the demand of each application.

Purely Software-Implemented Fault-Tolerant Techniques

Software-Based Fault-Tolerant Techniques Considering Hardware

Findings

Discussion

Conclusions