Single event transient sensitivity analysis of different 32 nm CMOS majority voters designs

Abstract

As a consequence of the technology scaling, the reduced amount of energy needed to store information impacts the Linear Energy Transfer Threshold (LETth), implying in circuits more sensitive to radiation faults. Hardware redundancy techniques such as the Triple Modular Redundancy are constantly used to mitigate this problem. However, the weakness of the redundancy technique is the voter circuit, and for this reason, alternative designs have been proposed in the literature to improve the robustness of this block. This work investigates the robustness of different majority voter topologies in the presence of Single Event Transient (SET). A layout-level analysis using stick diagrams is fulfilled to analyze the impact a SET causes in diffusion areas shared by transistors, and a fault masking ratio is used to measure the voter robustness. Then an electrical-level analysis was done based on the information provided from the previous study to investigate the threshold LET. The results obtained in this study shown that the topologies can endure a LET up to 1.86 MeV·cm−2/mg considering the 32 nm CMOS technology.