A Fault Tolerant Voter Circuit for Triple Modular Redundant System

Mohammed Hadifur Rahman

doi:10.11648/j.jeee.20170505.11

Abstract

Defect rate in Nanoelectronics is much higher than conventional CMOS circuits. Hardware redundancy can be a suitable solution for fault tolerance in nano level. A voter circuit is a part of a redundancy based fault tolerant system that enables a system to continue operating properly in the event of one or more faults within its components. Robustness of the voter circuit defines the reliability of the fault tolerant system. This paper provides simulation results and analysis of a fault tolerant voter circuit. In a Triple Modular Redundant (TMR) system, the robustness of the voter circuit has been improved. For this purpose, redundancy at transistor level has been added. In this technique each transistor of the various building blocks (Ex-OR gate, Multiplexer) of the voter circuit is replaced by a quadded-transistor structure. Quadded transistor structure provides built in immunity to all single defects as well as a large number of multiple defects. To evaluate the effectiveness of the voter circuit an IC layout in 90nm CMOS technology is developed. FPNI layout using qNAND hypercell is also designed and analysed. By simulation procedure it has been shown that the proposed fault tolerant voter circuit works properly as a majority voter in different faulty conditions of a TMR system. Moreover, it has been shown that in the presence of internal hardware failure (failure in transistor level) the voter circuit works properly.

Highlights

In nano-electronics the method of fabrication is very diferent
This paper presents a promising fault tolerant technique for majority voter circuit used in Triple Modular Redundancy (TMR)
The schematic of this quadded structured NAND gate and its block diagram is drawn by a commercial software DSCH, as shown in figure 4. (d) Using this qNAND the schematic diagram of an Ex-OR gate and a multiplexoris drawn as shown in figure 5. (e) Using these qEx-OR and qMUX circuit the schematic of desired voter circuit is made as shown in figure 5. (f) From the schematic of the voter circuit, the Verilog code is obtained. (g) Compiling the Verilog, IC layout of the proposed voter circuit is gained as shown in Figure 6. (h) the spice simulation is performed in the environment of the Commercial software Microwind

Summary

Introduction

In nano-electronics the method of fabrication is very diferent. Nano-electronics circuit is a regular structure generated by a stochastic self-assembly process. Stochastic self-assembly means that ICs will be fabricated with little or no outside intervention. Due to lack of outside intervention nano fabrication is more prone to defects. Some fault tolerance techniques can handle both defects and transient faults through hardware redundancy. [18] determines a large rectangular region that is devoid of any such defects. For a given technique a given percentage of faults can be mitigated whenever they may occur. Such a sub-crossbar region can be reliably used for mapping

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