FPGA implementation of area-efficient single precision floating point complex divider with fault detection

Abstract

Despite the applications of complex division in many fields like signal processing, control theory, telecommunication, etc., complex division algorithms are often treated with least importance. Most of the complex division modules are to be used in environments where fault-tolerance is required. FPGA is considered as a major candidate to implement such computationally intensive tasks because of its inherent properties. Interconnect faults and logic faults are two of the major types of faults likely to occur in FPGAs. Most of the existing works on fault-tolerant complex division uses hardware redundancy technique. This work proposes a technique to implement a complex division module with fault detection capability on FPGA. A module reuse technique is used to make the architecture area-efficient. The operands are being represented in 32-bit single precision floating point format.