Global Interconnects Research Articles

Frequency-domain analysis of CMOS-driven interconnects utilizing doped multilayer graphene nanoribbons and mixed carbon nanotube bundles

A frequency-domain model is developed to analyze isolated interconnects of multilayer graphene-nanoribbon (MLGNR) and mixed carbon-nanotube bundle (MCB) driven by CMOS gates. The model derived is founded on an equivalent-single-conductor model of MLGNR and MCB that takes thermal considerations into account (i.e. TD-ESC). The model includes the derivation of transfer function of interconnect to estimate its delay and bandwidth performance. The attained results, reveals that among the neutral MLGNR (N-MLGNR), intercalation doped MLGNR (ID-MLGNR) intercalated with FeCl3, MCB and Cu interconnects, FeCl3 ID-MLGNR achieves the best bandwidth efficiency. At a global interconnect length of 1 mm, FeCl3 ID-MLGNR outperforms N-MLGNR, MCB, and Cu in terms of bandwidth with an improved bandwidth value of 12.2 GHz, 7 GHz, and 61.4 GHz, respectively. Further, employing the proposed CMOS-gate-driven model, for FeCl3 ID-MLGNR, bandwidth is improved by nearly 7.52 × at global length (∼1 mm) in relation to the linear resistance model. Additionally, TD-ESC dependency of the proposed model reveals that FeCl3 ID-MLGNR becomes more stable as interconnect resistance increases.

Modeling and analysis of crosstalk induced effects in graphene-carbon nanotube composite interconnects

This paper proposes an equivalent circuit model for two-line coupled multilayer graphene nanoribbon - single-wall carbon nanotube (MLGNR-SWCNT) composite interconnects (MSCs), incorporating the effects of coupling capacitance and mutual inductance. We also examine the temperature-dependent crosstalk effect on the victim line of MSCs in the time domain using decoupling techniques and the ABCD parameter matrix approach. This analysis is conducted at the global level of 7 nm, 14 nm, and 22 nm technology nodes, comparing the performance of MSCs with MLGNR, SWCNT, and copper (Cu) interconnects, validated through HSPICE simulations. Our results reveal that the crosstalk delay of all interconnects induced by dynamic crosstalk exhibits superior performance in the in-phase crosstalk mode compared to the out-of-phase mode at room temperature. In particular, MSCs demonstrate less crosstalk delay in both crosstalk modes compared to SWCNT and Cu interconnects. In addition, we analyze the crosstalk delay of the victim line for two-line coupled MSCs at varying temperatures in out-of-phase crosstalk mode, comparing them with MLGNR, SWCNT, and Cu interconnects. Simulation results indicate that the crosstalk delay is temperature-dependent, increasing with rising temperatures, and the crosstalk delay of MSCs is the least of all interconnects. Furthermore, we investigate the crosstalk noise of MSCs induced by functional crosstalk at different temperatures, comparing it with MLGNR, SWCNT, and Cu interconnects. It is observed that the crosstalk noise peak remains constant with temperature changes across all interconnects; however, the holding time and width of crosstalk noise increases with rising temperatures and MSCs have the least crosstalk noise peak and crosstalk noise width of all interconnects. Also, numerical results exhibit that reducing interconnect temperature, SWCNT diameter, and edge roughness of MLGNR are effective strategies to diminish the crosstalk delay of MSCs. In addition, increasing line spacing is identified as an effective method to reduce crosstalk noise peak of MSCs of different lengths. The proposed model results show excellent agreement with HSPICE simulation data. Therefore, our analysis of crosstalk effect manifests that MLGNR-SWCNT composite can be a promising material to replace SWCNT and copper as an ideal material for global interconnect applications in thermally variable environments.

Estimation of bandwidth, voltage swing and DC coefficients for VLSI interconnects: current mode technique

ABSTRACT Necessity of bandwidth requires the effective use of it for high speed data transmission and faster read/write operation in memory cells. In this paper the transfer function expressions for RC interconnect line is presented for resistive load. The line delay, bandwidth and step response for current and voltage mode signalling is formulated. The current mode and voltage mode signalling provides the 3-dB bandwidth of 6.8 GHz and 3.1 GHz, respectively. An interconnect line modelled as either RLC or RC line depending upon input signal rise time, damping, and range of interconnect length with significant inductance effect is investigated for global interconnect lines. Low swing for column bit line in memory architectures is very important and estimated in terms of dc coefficients. For RC global interconnect of 10 mm, a swing of 0.382 V is obtained for current mode signalling, when a power supply of 1.8 V is applied to the network. DC coefficient and steady state value has been obtained which is significant for power computation on column bit line. It is also analytically validated by SPICE and MATLAB simulations.

Global RC Interconnects with ADL Buffers for Low-Power Applications

Introduction: Interconnects are an essential requirement for any circuit completion. They are utilised to connect two or more blocks, yet when creating a circuit, certain problems have been observed. Scaling back technology is one such problem. Methods: With technology scaled down their aspects change which can straightforwardly affect the circuit boundaries. Because of this, the time constant and power consumption in the interconnect circuits has increased. Certain wire (RC) models and techniques have previously been characterized to control these performance parameters however in this paper, authors have proposed a new interconnect structure with a buffer insertion technique using adiabatic dynamic logic (ADL). Results: To optimise power, a Schmitt trigger is inserted as a buffer between lengthy interconnect circuits utilising an energy-recovery mechanism. The TSPICE tool is used to model and simulate the entire circuit. Conclusion: The suggested model's performance is compared to that of other cutting-edge methods.

Design of Global RLC Interconnect Circuit with Analytical Delay Model

Background: With the advancement in technology nodes and scaling trends, the majority of the device performance depends upon the interconnections made between two or more devices. With these scaling trends, frequency plays a vital role. As the technology decreases, frequency tends to rise to giga-hertz. This increase in frequency gives rise to inductance parameters in the interconnect circuits. For long wires, the inductive impedance can become comparable to the resistive component due to which performance degradation can be observed along with overshoot and crosstalk issues that can no longer be ignored. Method: This article aims to examine the delay model and reconstruct an interconnect circuit that serves as a transmission line, ranging in length from 1 mm to 10 mm. Result: By keeping the frequency high, low voltage and rise/ fall time, performance parameters such as delay, power consumption, and overshoot are observed. Conclusion: The interconnect structure is compared with another state-of-the-art technique.

Quantum-Secure Signalling Model for L1/L2 Next-Gen Interconnect and Roaming Networks Over IPX for NB-IoT Traffic: A Review

Signalling security is critical for next-generation mobile (NGN) networks to ensure integrity, privacy, and confidentiality of communication protocols. However, recent research on existing 5G standards has uncovered vulnerabilities that could be exploited by emerging surveillance threats such as HiddenArt and Harvest Now Decrypt Later (HNDTL), as well as the prospect of quantum computing threatening to break classical cryptographic techniques. This systematic literature review (SLR) investigates quantum-based signalling solutions to mitigate these threats in interconnect and roaming 5G networks (IRN) over IP eXchange for Narrowband Internet of Things (NB-IoT) traffic. A database search was conducted, studies were selected and compared based on methods, approaches, techniques, and limitations. The SLR found that quantum key distribution (QKD) combined with quantum teleportation (QT) can protect and mitigate threats and attacks on signalling networks when protocols interact and interoperate in carrier networks. QKD techniques can be used for L1 protocols, while secure direct quantum communication can be used for L2 protocols. This study concludes that further studies are needed to integrate different techniques and protocols for L1/L2 signalling networks to create a robust quantum-secure signalling model for global interconnect and roaming NGN.

Energy Optimization for RC and RLC Interconnect Design in Low Power VLSI

Background: The global RC interconnects have become the controlling parameter for a circuit’s performance. But with the decrease in technology, an increase in resistance has become prominent. This increase further directly affects the performance of the system by increasing the performance parameters of the circuit like delay and power consumption. To resolve this issue and to be compatible with Internet of Things (IoT) applications, the interconnect circuits are required to be high speed with less heat generation. Methods: In this paper, a new RC and RLC interconnect circuit design was proposed for 45 nm technology to enhance the performance parameters. Furthermore, the RC interconnect design was simulated for lumped and distributed networks. The parasitic component values (resistance, inductance, and capacitance) are evaluated using PTM technology. Results: The proposed interconnect circuit's resistance value decreased by a factor of 4, but the capacitance remains the same. Furthermore, power consumption and delay values were attained. An overall comparison was done between RC and RLC networks. Conclusion: 63.13% power improvement and 24.87% delay improvement were observed in the RLC network over RC distributed network.

Variable Length and Temperature-Dependent Analysis of MLGNR at Nano-Scale Regime

In this paper, a thermally aware equivalent single conductor is proposed, along with analytical modeling to evaluate the parasitic parameters of multilayer graphene nanoribbon (MLGNR) as interconnect, and its performance is analyzed in terms of delay and power delay product (PDP) for 32[Formula: see text]nm, 22[Formula: see text]nm and 16[Formula: see text]nm technology nodes at variable global interconnect lengths (500–2000[Formula: see text]m). It was examined that with rising temperature, there is a strident decrease in the mean free path (MFP) of GNR interconnect, which further influences its own resistance at global length (2000[Formula: see text][Formula: see text]m) for all three technology nodes. The simulation tool Simulation Program with Integrated Circuit Emphasis (SPICE) is used to estimate and compare MLGNR performance in terms of signal delay and PDP for three different technology nodes. It is revealed from the outcomes that the propagation delay and PDP increase at long interconnects (500–2000[Formula: see text][Formula: see text]m) over a temperature range of 200–500[Formula: see text]K for deep submicron technology nodes (16[Formula: see text]nm, 22[Formula: see text]nm and 32[Formula: see text]nm). A similar investigation was performed on the copper interconnect, and it was discovered that the MLGNR performs better in terms of delay and PDP at global levels with a temperature range of 200–500[Formula: see text]K for nano-scaled technology nodes (32[Formula: see text]nm, 22[Formula: see text]nm and 16[Formula: see text]nm).

Heterogeneous Integration with 3D Packaging

The next generation of competitive integrated devices demand increased device density, higher memory bandwidth, reduced global interconnects, increased energy efficiency (with higher performance), and a smaller footprint. With the slowdown in Moore’s law and the advancements in chiplet architectures, which are now recognized as fundamental to enabling the continued economically viable growth of power efficient computing, advanced packaging technologies and architectures are becoming more critical to enabling Moore’s Law’s next frontier through heterogeneous integration. In this presentation, we will cover the advanced package architectures being enabled by AMD to enable power, performance, area, and cost (PPAC) improvements as well as enable heterogeneous architectures. The direct Cu-Cu bonding technology used in AMD 3D V-Cache architecture will be detailed and compared to industry standard 3D architectures.

Modeling and performance analysis of coupled multilayer graphene nanoribbon (MLGNR) interconnects with intercalation doping

This paper investigated the temperature‐dependent performance of coupled top contact multilayer graphene nanoribbon interconnects (TC-MLGNRs) with different intercalation doping (viz., AsF5-, FeCl3-, and Li-doped) considering edge roughness and crosstalk effect, compared with SC-MLGNR, MWCNT, and copper (Cu) interconnects for 13.4 nm technology nodes at the global level. Based on the equivalent single conductor (ESC) modeling, a distributed transmission line model for coupled doped TC-MLGNRs is presented to obtain the crosstalk delay, step response, transfer gain, and 3-dB bandwidth, which considers in-phase and out-of-phase crosstalk modes and verified with the Hspice simulation. It is demonstrated that all interconnects at room temperature in the in-phase crosstalk mode outperform those in the out-of-phase crosstalk mode in terms of crosstalk delay, transfer gain, and 3-dB bandwidth, and Li-doped TC-MLGNR significantly reduces crosstalk delay and enhances transfer gain and 3-dB bandwidth compared to other interconnects. Moreover, it is found that the victim line of two-line coupling for doped TC-MLGNRs exhibits less crosstalk delay, greater transfer gain, and 3-dB bandwidth compared to the center line of three-line coupling for doped TC-MLGNRs in the same condition. Furthermore, we analyze the crosstalk delay and 3 dB-bandwidth for two- and three-line doped TC-MLGNRs at varying temperatures and compare them with SC-MLGNR, MWCNT, and Cu interconnects. Simulation results show that crosstalk delay and bandwidth performance are temperature dependent, and they both degrade with increasing temperature. Also, Li-doped TC-MLGNRs still exhibit the best crosstalk delay and bandwidth performance of all interconnects. The numerical calculation results show that decreasing interconnect temperature, increasing line spacing, and reducing edge roughness are efficient methods to reduce crosstalk delay and enhance 3-dB bandwidth for Li-doped TC-MLGNRs. In addition, the results obtained by the proposed model are well matched with the Hspice simulation. Hence, our performance analysis demonstrates that Li-doped TC-MLGNR can be a promising material for global interconnect applications in a thermally variable environment.

NeuSB: A Scalable Interconnect Architecture for Spiking Neuromorphic Hardware

Neuromorphic systems are typically designed as a tile-based architecture where inter-tile data communication is facilitated using a shared global interconnect. Congestion on this interconnect can increase both interconnect energy, which increases the total energy consumption of the hardware and latency, which impacts the performance e.g., accuracy of the application that is being executed on the hardware. Mesh-based Network-on-Chip (NoC) that is used in most hardware prototypes is not the optimal interconnect solution for neuromorphic systems. This is because of the following two reasons. First, power consumption and average latency of a NoC increases exponentially with the number of tiles in the hardware. Second, a NoC cannot exploit an application’s data communication pattern efficiently. Once designed for a target hardware, the bandwidth on each NoC link stays the same, independent of the volume of data traffic between different tile pairs of the NoC. In other words, a NoC cannot be customized at a finer granularity based on an individual application running on the hardware. We show that these NoC limitations prevent opportunities to further improve energy and latency of a neuromorphic hardware. To address these limitations, we propose Dynamic Segmented Bus (SB) interconnect for neuromorphic systems. Here, a bus lane is partitioned into segments with each segment connecting a few tiles. Connection of tiles to segments and those between segments are bridged using our novel three-way segmentation switches that are programmed using the software before admitting an application to the hardware. We partition an application by analyzing its workload and place partitions intelligently onto segments. This exploits application characteristics to use the segments without any routing collisions while exploiting the latency and energy savings in the design-time mapping phase. At a high-level, our mapping algorithm places tiles that communicate the most on shorter segments utilizing fewer number of switches, thereby reducing network congestion. It can adjust the bandwidth by controlling the number of segments connected to a destination tile. At run time, our controller dynamically executes the predefined routing paths without requiring any additionally routing decisions, unlike a NoC. This allows us to improve both energy and latency. Using parallel segmented busses, our proposed interconnect architecture can support a large number of tiles without significantly increasing the design cost, energy, and latency. Simulation results show that compared to the most widely-used mesh-based NoC design, our interconnect architecture, which we call NeuSB, reduces the switch area by 20x, average interconnect energy by 6.2x, and latency by 23%.

Impact of functional crosstalk on mixed CNT bundles for future VLSI nodes

This paper focuses on a novel class of interconnect material employed in integrated circuits at nanotechnology nodes called as mixed CNT (carbon nanotube) bundle structures. These mixed bundle structures are formed by changing different positions of multi-wall and double-wall CNTs. The impact of temperature on the performance of global interconnects and the effect of undesirable functional crosstalk is also presented in detail. Crosstalk has been studied by performing transient analysis of MDCB (multi-walled CNT and double-walled CNT bundles) structures to evaluate their performance in relation with signal functionality.

Delay analysis of mixed CNT bundles as global interconnect for nanotechnology nodes

Abstract This paper presents modeling of high current capability of mixed carbon nanotube (CNT) bundle interconnects depending upon the type of constituent CNT materials and their orientations. With different arrangements, one category of novel mixed CNT bundles formed by the combination of multi-walled/multi-shell CNT and double-shell CNT bundles (MDCB) are proposed and compared with the mixed CNT bundles (MSCB) formed with multi-shell CNT and single-walled CNT bundles. A time-domain analysis is performed for these structures to analyse the effect of delay and power dissipation. It has also been observed that MDCB structures give better performance (≈ 30%) than MSCB structures in terms of power-delay product at the global length of interconnect for nano-regime technology nodes. Also, MDCB structure formed by placing multi-walled CNTs along the periphery and double-walled CNTs in the centre of structure yields the best result against all proposed mixed CNT bundled structures and can be employed for future interconnect applications.

Crosstalk Peak Overshoot Analysis of VLSI Interconnects

As technology extended from deep sub-micron technology to nanometer regimes, the conventional copper (Cu) wire will not be able to continue. Now a substitute approaches such as Carbon Nano Tube (CNT) interconnects have been suggested to ignore the problems associated with global interconnects. Hence in this work, crosstalk analysis of Complementary metal oxide semiconductor (CMOS) buffer-driven of different interconnects have been analyzed for peak overshoot and overshoot width of Cu and CNTs for 16nm technology. For analyzing peak overshoot, the interconnect lengths are varied from 100um to 500um in 16 technology node for Cu, single walled carbon nanotube (SWCNT) and multi-walled carbon nanotube (MWCNT). The values of the peak overshoot and overshoot width changes, as the interconnect length increases, the peak overshoot and width is going to be increases. As Compared to Cu, SWCNT and MWCNT, the peak overshoot and width for SWCNT is lesser than copper and MWCNT. The MWCNT interconnect is less than that of conventional Copper interconnects.

Analysis of Crosstalk in GNR-Based Global Interconnects

Analysis of Crosstalk in GNR-Based Global Interconnects

Frequency response analysis of CNT bundle interconnects

ABSTRACT When carbon nanotubes (CNTs) are used in interconnects, their electrical properties are appealing as they are not affected by surface scattering when the feature size decreases. After almost two decades of research on CNT-based interconnects, it is still a question which type of CNT bundle performs better than the other. There are many contradictory reports in this regard. So, it is very important to study the frequency response of these interconnects to ascertain their actual performance and compare them. HSPICE-based circuit simulations at 20 nm and 14 nm technology nodes are carried out. Furthermore, the analysis for local, semi-global and global interconnect lengths is carried out. Results show that single-walled CNT (SWCNT) bundles have higher voltage gain and higher current gain for all lengths at both the technology nodes. These results are significant in understanding the best choice of interconnects among SWCNT bundle, MWCNT bundle and mixed CNT bundle interconnects.

Analytical Delay Model and Stability Analysis for MLGNR Interconnects

This paper analyzes the signal delay and relative stability of multilayer graphene nanoribbon (MLGNR) interconnects dependent on temperature at global lengths. A thermally aware driver interconnect load (DIL) system, constituted by equivalent single conductor (ESC) model along with mathematical equations, is proposed to convert multi-conductor transmission circuit into single transmission line of MLGNR. The temperature-dependent analytical delay model of MLGNR is evaluated and the obtained outcomes are compared with the simulated results. The analytical and simulated results are obtained at global interconnect length (2000-[Formula: see text]m) for 32[Formula: see text]nm, 22[Formula: see text]nm and 16[Formula: see text]nm nodes of technology under 200–500[Formula: see text]K temperature range of MLGNR. The simulation and analytical results reveal that the outcomes of the two models correspond well. The trend of the models shows the increase in delay with the rising temperature levels (200–500[Formula: see text]K) for three different nodes of technology. Further, relative stability analysis of MLGNR as interconnect line at three different technological nodes from 500–2000-[Formula: see text]m lengths is examined.

Performance Analysis of CNT Bundle Interconnects in Various Low-k Dielectric Media

The capacitance of the interconnect, which contributes to RC delay, power, and crosstalk, is increasingly limiting the performance of ULSI chips as IC technology advances. Different dielectric materials are employed as electrical shielding between interconnects (also called as inter-wire dielectrics) to minimise the coupling capacitance of closely spaced interconnects, and they are compared in terms of their performance. For SWCNT and MWCNT interconnects at various global interconnect lengths for 20 nm and 14 nm technology nodes, performance parameters such as crosstalk delay, power dissipation, power crosstalk delay product (PCDP) and crosstalk noise are calculated and compared. It is observed that, upon using different dielectric materials in CNT bundle interconnect, MWCNT bundle interconnects is performing better compared to SWCNT bundle interconnects at 20 nm and 14 nm technology nodes for all global interconnect lengths.

Design of DG FinFET based driver circuits for energy efficient sub threshold global interconnects

Design of DG FinFET based driver circuits for energy efficient sub threshold global interconnects

Design and performance analysis of buffer inserted on-chip global nano interconnects in VDSM technologies

Design and performance analysis of buffer inserted on-chip global nano interconnects in VDSM technologies