Energy Optimization for RC and RLC Interconnect Design in Low Power VLSI

Abstract

Background: The global RC interconnects have become the controlling parameter for a circuit’s performance. But with the decrease in technology, an increase in resistance has become prominent. This increase further directly affects the performance of the system by increasing the performance parameters of the circuit like delay and power consumption. To resolve this issue and to be compatible with Internet of Things (IoT) applications, the interconnect circuits are required to be high speed with less heat generation. Methods: In this paper, a new RC and RLC interconnect circuit design was proposed for 45 nm technology to enhance the performance parameters. Furthermore, the RC interconnect design was simulated for lumped and distributed networks. The parasitic component values (resistance, inductance, and capacitance) are evaluated using PTM technology. Results: The proposed interconnect circuit's resistance value decreased by a factor of 4, but the capacitance remains the same. Furthermore, power consumption and delay values were attained. An overall comparison was done between RC and RLC networks. Conclusion: 63.13% power improvement and 24.87% delay improvement were observed in the RLC network over RC distributed network.