Low Power Repeaters Driving RLC Interconnects with Delay and Bandwidth Constraints

Abstract

Interconnects play an increasingly important role in deep submicrometer VLSI technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. The effects of inductance on the delay, bandwidth, and power of an RLC interconnect with repeaters are analyzed. A repeater insertion methodology is presented for achieving the minimum power in an RLC interconnect while satisfying delay and bandwidth constraints. By including inductance, the minimum interconnect power under a delay and/or bandwidth constraint decreases as compared with an RC interconnect.