Gate-all-around Research Articles

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices.

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

Variability characteristics and corner effects of gate-all-around (GAA) p-type poly-Si junctionless nanowire/nanosheet transistors

In this paper, we experimentally examined the threshold voltage (V T) variability and the corner effects in gate-all-around p-type poly-Si junctionless (JL) nanowire (NW) and nanosheet (NS) transistors as a function of various effective channel width. The fabricated devices showed small V T variability characteristics even in poly-Si JL NW channel structure thanks to the improved quality of poly-Si channel by fluorine (F) passivation and reduced channel concentration by boron (B) segregation. In addition, it was found by examining the corner effects that the fabricated devices exhibit accumulation-mode like behaviors. The origins of these phenomena are discussed.

A Steep-Slope MoS2/Graphene Dirac-Source Field-Effect Transistor with a Large Drive Current.

In the continuous transistor feature size scaling down, the scaling of the supply voltage is stagnant because of the subthreshold swing (SS) limit. A transistor with a new mechanism is needed to break through the thermionic limit of SS and hold the large drive current at the same time. Here, by adopting the recently proposed Dirac-source field-effect transistor (DSFET) technology, we experimentally demonstrate a MoS2/graphene (1.8 nm/0.3 nm) DSFET for the first time, and a steep SS of 37.9 mV/dec at room temperature with nearly free hysteresis is observed. Besides, by bringing in the structure of gate-all-around (GAA), the MoS2/graphene DSFET exhibits a steeper SS of 33.5 mV/dec and a 40% increased normalized drive current up to 52.7 μA·μm/μm (VDS = 1 V) with a current on/off ratio of 108, which shows potential for low-power and high-performance electronics applications.

Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs

A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band structure experimentally. In addition, the pronounced ballistic transport characteristics were demonstrated in the GAA Si NW MOSFET. Due to the existence of spacers for the typical MOSFET, the quantum interference was also successfully achieved at lower bias.

2-D-Nonlinear Electrothermal Model for Investigating the Self-Heating Effect in GAAFET Transistors

The objective of the present study is to analyze the heat transfer in the gate-all-around (GAA) MOSFETs based on the Cattaneo and Vernotte (CV) model due to the finite heat propagation speed in these nanodevices. The derivation of the CV model from the Boltzmann transport equation (BTE) is presented. Using the finite-element method, the nonlinear heat conduction model coupled with Poisson and continuity equations has been numerically solved to predict the self-heating effect (SHE) in GAA MOSFET. The CV model is applied in several structures, namely, single-metal surrounding gate (SMSG), dual-metal surrounding gate (DMSG), and triple-metal surrounding gate (TMSG). The obtained results are also compared with those calculated with the Fourier law. The temporal evolution and spatial distribution of the temperature and heat flux have been investigated. It is seen that the oscillatory behavior of the temperature using the CV model is strengthened for the TMSG structure and by increasing the relaxation time. Furthermore, the TMSG structure leads to an important increase in the temperature inside the device.

Analysis of Circuit Simulation Considering Total Ionizing Dose Effects on FinFET and Nanowire FET

In this study, we analyzed the total ionizing dose (TID) effect characteristics of p-type FinFET and Nanowire FET (NW-FET) according to the structural aspect through comparison of the two devices. Similar to n-type devices, p-type NW-FETs are less affected than FinFETs by the TID effect. For the inverter TID circuit simulation, both n- and p-types of FinFET and NW-FET were analyzed regarding the TID effect. The inverter operation considering the TID effect was verified using the Berkeley short-channel insulated-gate FET model (BSIM) common multi-gate (CMG) parameters. In addition, an inverter circuit composed of the NW-FET exhibited a smaller change by the TID than that of an inverter circuit composed of the FinFET. Therefore, the gate controllability of the gate-all-around (GAA) device had an excellent tolerance to not only short-channel effects (SCE) but also TID effects.

Design of Dopingless GaN Nanowire FET with Low ‘Q’ for High Switching and RF Applications

The unique properties like wide band gap and high electron mobility makes GaN an interesting material to be used in building devices at the nanoscale in recent times. This paper first time proposed a charge plasma (CP) based dopingless gate all around (GAA) GaN Nanowire FET (NWFET) (CP-GaN). The advantages of CP device over junctionless (JL) in NWFET structure along with properties of GaN material, results in a highly efficient structure of CP-GaN. The CP-GaN is compared with JL-GaN and silicon counterparts of CP & JL. Results reveal that CP-GaN is showing outstanding performance as Ion of 3.95 × 10−5 A, Ioff of 5.36 × 10−13 A and Ion/Ioff of 7.37 × 107. The proposed device CP-GaN shows better performance than CP-Si based device. When compared with JL-GaN, CP-GaN shows 55% less DIBL. The figure of merit Q = gm/SS of 0.85 μS/μm-dec/mV, is highest for our proposed CP-GaN. This makes CP-GaN an attractive design to be explored for high switching & low voltage applications with reduced SCEs and lower thermal budget. The other design parameters viz. gate length, gate dielectric, gate and source/drain work functions, nanowire radius and interface trap charges effect are also investigated for further optimization of the proposed design.

Nanowire Array-based MOSFET for Future CMOS Technology to Attain the Ultimate Scaling Limit

Silicon nanowire (SiNW) structures are the essential foundations of the next generation highly efficient and lowcost electronic devices because of their specific chemical, optical, and electrical properties. In recent decades, the production of pure Si NW arrays with the ability to tune the wire density and dimensions has been intensively studied. This paper demonstrates the performance of silicon nanowire (Si NW) array based cylindrical gate all around (GAA) MOSFET using quantum transport model in lower technology nodes. With an improvement in drain current and lower value of threshold voltage, the proposed structure is proving itself as one of the leaders in GAA MOSFET family. Again the study includes the effect of variation in gate voltage on the electrostatic potential of individual nanowires and the potential developed at the channel-source/drain interface. The improved ON current with superior electrostatic integrity due to silicon pillars is showing the possibility of this device towards future development in CMOS technology. Finally, the article includes the integration of nMOS and pMOS to realize the CMOS inverter for high speed and noise immune characteristics.

Design and Analysis of Gate Overlapped/Underlapped NWFET Based Lable Free Biosensor

In this paper, gate all around (GAA) nanowire P-channel FET label free biosensor is proposed with cavity. Proposed structure is label free so it doesn’t require selective material for specific biomolecule enzymes. High surface to volume ratio provide good sensitivity which is crucial for any biosensor application. To sense the kind of biomolecule, there is a cavity created at the gate, so biological elements like enzymes interact with cavity and it changes the carrier concentration which in turn changes the current. In addition to this, first biosensor structure is analyzed with cavity at the source side and second structure is analyzed with cavity at the drain side. Length of cavity is varied from 10 nm to 40 nm for optimization of the proposed biosensor structure. This biosensor is used to find the amount of biomolecule present in aqueous solution through their enzymes. To estimate the sensing capability of this sensor, testing is done using glucose molecules. We observed comparatively better sensitivity when cavity is placed at drain side.

Study and Analysis of Advanced 3D Multi-Gate Junctionless Transistors

As the IC technology is evolving very rapidly, the feature size of the device has been migrating to sub-nanometre regime for achieving the high packing density. To continue with further scaling of ICs, some novel devices such as multiple-gate silicon-on-insulator (SOI) devices, Gate-All-Around (GAA) nanowire and Nanotube MOSFETs have been proposed by researchers in recent years. The short channel transistor below 10 nm needs to have ultra-sharp junctions at source and drain ends with the channel region. The creation of such a sharp junction is quite challenging process from fabrication point of view. Therefore, junctionless transistors (JLT) were proposed to eradicate junction’s related issues, exhibit full CMOS functionality. The multigate junctionless transistors have been proposed, designed and fabricated. This paper illustrated basic working mechanism and behaviour of the various single and multi-gate junctionless MOSFETs. Junctionless nanowires transistor with single circular gate and gate material engineered techniques has also been explained. From simulation results, it has been observed that junctionless Nanotube GAA MOSFET has shown superior electrical behaviour over the Nanowire GAA MOSFET. Junctionless GaAs-Nanotube MOSFET has shown tremendous response over Junctionless Si-Nanotube MOSFET in terms of leakage and ON current. Junctionless GaAs-Nanotube MOSFET may be observed as alternate candidate for future CMOS applications.

Tellurium Nanowire Gate-All-Around MOSFETs for Sub-5 nm Applications.

The nanowire (NW) and gate-all-around (GAA) technologies are regarded as the ultimate solutions to sustain Moore's law benefitting from the exceptional gate control ability. Herein, we conduct a comprehensive ab initio quantum transportation calculation at different diameters (single trigonal-tellurium NW (1Te) and three trigonal-tellrium NW (3Te)) sub-5 nm tellurium (Te) GAA NW metal-oxide-semiconductor field-effect transistors (MOSFETs). The results claim that the performance of 1Te FETs is superior to that of 3Te FETs. Encouragingly, the single Te (1Te) n-type MOSFET with 5 nm gate length achieves International Technology Roadmap for Semiconductors (ITRS) high-performance (HP) and low-dissipation (LP) goals simultaneously. Especially, the HP on-state current reaches 6479 μA/μm, 7 times higher than the goal (900 μA/μm). Moreover, the subthreshold swing of the n-type 1Te FETs even hits a thermionic limit of 60 mV/dec. In terms of the spin-orbit coupling effect, the drain currents of devices are further improved, particularly the p-type Te FETs can also achieve the ITRS HP goal. Hence, the GAA Te MOSFETs provide a feasible approach for state-of-the-art sub-5 nm device applications.

Silicon Nanowire Parameter Extraction Using DFT and Comparative Performance Analysis of SiNWFET and CNTFET Devices

The performance and scalability of silicon nanowire field-effect transistor (SiNWFET) and carbon nanotube field-effect transistor (CNTFET) with surround gate geometry were studied using such tools as material exploration and design analysis (MedeA) and device modeling and simulation SilvacoTCAD. The SiNWFET and CNTFET with gate-all-around (GAA) structure offer good gate electrostatic control, high On-current and better suppression of short-channel effects with complete encirclement of the device channel. Rather than using the bulk properties of silicon, estimation of properties silicon nanowire (SiNW) was made using MedeA VASP tool based on density functional theory (DFT). In this study, the device input (ID–VGS) and output (ID–VDS) have been analyzed and parameters like threshold voltage, IOn/IOff ratio, drain induced barrier lowering and sub-threshold slope extracted, and comparison is made between SiNWFET and CNTFET devices. The results point towards the DFT-based material parameter estimation to incorporate the quantum effects and use of SiNW/CNT-based GAA structure below 10 nm to meet scaling targets. The results suggest that the SiNWFET and CNTFET device with GAA geometry could be a better alternative to conventional MOSFETs and FinFET for numerous high-performance and low-power device applications.

Ultrathin Sub-5-nm Hf₁₋ₓZrₓO₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate

This study investigates a device’s ability to boost its on-state current and subthreshold behavior using a ferroelectric field-effect transistor (FeFET) with an ultrathin sub-5-nm Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-<i>x</i></sub> Zr <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> O2 (HZO). A conventional field-effect transistor (FET) with pure hafnium (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) is used as a control measure and the impact of an internal metal gate (IMG) is also discussed. The study was conducted by using a sub-5-nm HZO and seed layer to fabricate a gate-all-around (GAA) nanowire (NW); a FeFET with a metal-ferroelectric–metal-insulator-semiconductor (MFMIS) structure; and a double layer (DL) of the channel. The channel size used in the experiment was approximately <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9.6\times16$ </tex-math></inline-formula> nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the total thickness of the gate stack was 9.2 nm. This thickness is 50.5% less than our previous experiment. The FeFET exhibits a considerably high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{on}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{off}$ </tex-math></inline-formula> ratio exceeding 107. The IMG serves as a potential equalizer and the ferroelectric material is arranged in a more symmetrical electric field. This results in a lower subthreshold (sub- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{TH}$ </tex-math></inline-formula> ) swing ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S.S._{min}=$ </tex-math></inline-formula> 49.3mV/decade) with a wide range ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{3}$ </tex-math></inline-formula> ) of drain currentcompared to that without an IMG. The findings indicate that a high-performance GAA FET can be achieved by combining a DL channel, GAA NW, ferroelectric material, and an IMG.

Performance Analysis of Gate All Around (GAA) MOSFET at Cryogenic Temperature for the Sub-Nanometer Regime

Performance Analysis of Gate All Around (GAA) MOSFET at Cryogenic Temperature for the Sub-Nanometer Regime

Capacitance model for nanowire gate-all-around tunneling field-effect-transistors

The nanowire gate-all-around (GAA) structures with the nearly ultimate channel electrostatic integrity of the gate field can exhibit the best immunity to the short channel effect and drain-induced barrier lowering. Moreover, owing to the enhanced control efficiency of gate over the tunneling junction, the GAA-TFET also gives improved subthreshold swing and on-state current. Despite the excellent device performance, an accurate model is very significant for the practical application. Compared with the numerical methods which are usually time consuming and computationally inefficient, an analytical model could accelerate the device investigation and circuit design process. Even though some tunneling current models have already been reported for nanowire tunneling field-effect-transistors (TFETs), the model of the terminal capacitance is still an issue for nanowire TFETs. The capacitance is of great significance for the transient simulation. In this paper, a physical and analytical potential model considering both the source depletion region and the channel mobile charges, is developed for the GAA-TFETs. The results from the model are verified with the numerical simulations, and the excellent agreement between the two results indicates the validation of the proposed model. Based on the potential model, the terminal charge model and the capacitance model are further developed and also verified by the numerical simulations. The main inflection and variation of the terminal charges and capacitances with the biases can be predicted by our model. Besides, both the model results and the numerical simulations both demonstrate that the gate charge is dominated mainly by the drain charges and the contribution of the source charges can be almost neglected. This also leads to the very small gate-source capacitance and very large Miller capacitance in the TFET device. This will be detrimental to the performance of TFET-based digital circuits but can be mitigated with the hetero-oxide gate structure. The second order effects, such as the quantum confinement and traps, are ignored in this paper and can be taken into the core model in the future work. It should also be noted that there is no iterative process involved during the model derivation, thus the developed model can be easily applied to the widely used SPICE platform and will be useful in designing and investigating the GAA-TFET based circuits.

A Simulation Study on the Effects of Interface Charges and Geometry on Vertical GAA GaN Nanowire MOSFET for Low-Power Application

The effects of interface charges on the performances of gate-all-around (GAA) GaN vertical nanowire MOSFETs with different geometries have been studied. Geometrical effect on the gate current of vertical GAA GaN nanowire MOSFET has also been analysed for the first time. In the ideal condition, the circular geometry nanowire (CGN) MOSFET exhibits the best performance with subthreshold swing (SS) of 62 mV/dec, drain-induced barrier lowering (DIBL) of 14 mV/V, and ON/OFF current ratio ( I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> . The triangular or hexagonal geometry nanowire (TGN or HGN) MOSFET suffer from large gate leakage current due to the field enhancement at sidewall corners. It is also known that interface traps at the sidewall surface of vertical nanowires deteriorate the overall device performance. The HGN MOSFET with m-plane sidewall demonstrates the best performance with SS of 69 mV/dec and DIBL of 13 mV/V, while the TGN MOSFET with a-plane sidewall exhibits the worst performance with SS of 112 mV/dec and DIBL of 101 mV/V.

Subthreshold Swing in Silicon Gate-All-Around Nanowire and Fully Depleted SOI MOSFETs at Cryogenic Temperature

Subthreshold swing (SS) in a silicon gate-all-around (GAA) nanowire MOSFET with zero body factor is examined from room temperature (RT) down to 4 K. A fully depleted (FD) SOI MOSFET is also evaluated. The values of SS of both transistors decrease in proportional to temperature (T) but start to saturate below 18K, similar to transistors with non-zero body factor in the literature, indicating that the body factor is not related to the SS saturation phenomena at very low temperatures.

Numerical Analysis of Gate-All-Around HfO2/TiO2/HfO2 High-K Dielectric Based WSe2 NCFET With Reduced Sub-Threshold Swing and High On/Off Ratio

Gate-all-around (GAA) field effect transistors (FETs) have appeared as one of the potential candidates for the electrostatic integrity required to reduce MOSFETs to minimum channel lengths. Meanwhile, the negative capacitance effect of ferroelectrics is known as a remarkable quality enhancer for MOSFETs in terms of reducing sub-threshold slope (SS), supply voltage, and power consumption by utilizing the gate voltage amplification phenomenon. In this work, combining these two phenomena we numerically design a cylindrical GAA NCFET where promising two-dimensional WSe2 is used as a channel material. We have suggested a high-K dielectric consisting of a tri-layer HfO2/TiO2/HfO2 and lead zirconate titanate (PZT) as a ferroelectric layer in the gate stacking. The extremely high $I_{on}/I_{off}$ ratio on the order of 1012 (six order higher than conventional FET), and the high on-state current of $119~\mu \text{A}$ are the most remarkable findings of this device which exceeds all the earlier results. The integration of the NC effect utilizing a 20 nm PZT offers lowest $SS$ of 18.9 mV/dec. Moreover, a large transconductance ( $g_{m}$ ) of $117~\mu \text{S}$ and a higher current cut-off frequency ( $f_{T}$ ) of 335 GHz were reported from the output characteristics. These outcomes allude that the suggested device structure may create a new path for electronic devices; therefore, it can be used for high speed operation with low power consumption.

Quantum Modelling of Nanoscale Silicon Gate-All-Around Field Effect Transistor

The paper introduces an analytical model for gate all around (GAA) or Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (SG-MOSFET) inclusive of quantum mechanical effects. The classical oxide capacitance is replaced by the capacitance incorporating quantum effects by including the centroid parameter. The quantum variant of inversion charge distribution function, inversion layer capacitance, drain current, and transconductance expressions are modeled by employing this model. The established analytical model results agree with the simulated results, verifying these models' validity and providing theoretical supports for designing and applying these novel devices.

(Invited) Vertical Gate All Around GeSn/Ge Heterostructure Transistors

In this paper we present our recent research on vertical GeSn/Ge heterojunction gate all around (GAA) nanowire pMOSFETs. The vertical nanowires were fabricated with a diameter as small as 20 nm. Our experimental results demonstrate that scaling of the nanowire diameter improves the device performance in terms of subthreshold swing, drain induced barrier lowering (DIBL) and Ion/Ioff ratio due to the better gate controllability. However, one of the big challenges for vertical nanowire transistors is the nanowire top contact resistance. Due to the very small contact area the nanowire contact resistance dominates the series source/drain resistance. The contact resistance can be lowered by optimized NiGeSn and NiGe contacts. Compared to vertical Ge homojunction nanowire GAA FETs, the utilization of GeSn as source can significantly lower the source/drain resistance. The band engineering of GeSn/Ge heterojunction for device improvement will be discussed in the paper.