(Invited) Vertical Gate All Around GeSn/Ge Heterostructure Transistors

Abstract

In this paper we present our recent research on vertical GeSn/Ge heterojunction gate all around (GAA) nanowire pMOSFETs. The vertical nanowires were fabricated with a diameter as small as 20 nm. Our experimental results demonstrate that scaling of the nanowire diameter improves the device performance in terms of subthreshold swing, drain induced barrier lowering (DIBL) and Ion/Ioff ratio due to the better gate controllability. However, one of the big challenges for vertical nanowire transistors is the nanowire top contact resistance. Due to the very small contact area the nanowire contact resistance dominates the series source/drain resistance. The contact resistance can be lowered by optimized NiGeSn and NiGe contacts. Compared to vertical Ge homojunction nanowire GAA FETs, the utilization of GeSn as source can significantly lower the source/drain resistance. The band engineering of GeSn/Ge heterojunction for device improvement will be discussed in the paper.