Abstract
The effects of interface charges on the performances of gate-all-around (GAA) GaN vertical nanowire MOSFETs with different geometries have been studied. Geometrical effect on the gate current of vertical GAA GaN nanowire MOSFET has also been analysed for the first time. In the ideal condition, the circular geometry nanowire (CGN) MOSFET exhibits the best performance with subthreshold swing (SS) of 62 mV/dec, drain-induced barrier lowering (DIBL) of 14 mV/V, and ON/OFF current ratio ( I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> . The triangular or hexagonal geometry nanowire (TGN or HGN) MOSFET suffer from large gate leakage current due to the field enhancement at sidewall corners. It is also known that interface traps at the sidewall surface of vertical nanowires deteriorate the overall device performance. The HGN MOSFET with m-plane sidewall demonstrates the best performance with SS of 69 mV/dec and DIBL of 13 mV/V, while the TGN MOSFET with a-plane sidewall exhibits the worst performance with SS of 112 mV/dec and DIBL of 101 mV/V.
Highlights
The continuous scaling of transistor demands the evolution of devices in terms of material and device structure
The Triangular geometry nanowire (TGN) MOSFET shows the lowest current drivability due to the deeply depleted channel at equilibrium because of the smaller cross-sectional area, which results in the highest VTH
It was proved that IG is strongly dependent on the gate geometry for the first time, especially at large VG where the gate electric field is higher
Summary
The continuous scaling of transistor demands the evolution of devices in terms of material and device structure. Many research works have demonstrated that the GaN-based nanowire devices, along with their material advantages, can show strong immunity. Studies on nanowire channels with different geometry, based on basic material parameters of GaN, have shown that MOSFET with triangular-shaped nanowire channel exhibits better performances [21], [22]. This work analyze the GAA GaN vertical nanowire MOSFET by considering the geometrical effect of the nanowire channel as well as the interface trap effects at corresponding sidewall planes of the nanowire channel for the first time. The effect of field enhancement in a nanowire of certain geometries such as triangular and hexagonal has never been studied. The interface trap effect based on the non-polar sidewall planes of nanowires of different geometry is analysed in depth
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