Gate Work Function Engineering Research Articles

Triple and quadruple metal gate work function engineering to improve the performance of junctionless double surrounding gate In0.53Ga0.47As nanotube MOSFET for the upcoming Sub 3 nm technology node

In line with Moore's Law and the International Roadmap for Devices and Systems (IDRS), shrinking MOSFET dimensions to the 3 nm technology node requires the introduction and thorough investigation of new device structures and advanced materials. The current study focuses on the implementation of Triple Metal (TM) and Quadruple Metal (QM) gate work function engineering techniques on both junctionless (JL) and inversion mode (IM) Double surrounding Gate (DSG) In0.53Ga0.47As nanotube (NT) MOSFET. The objective is to analyze the drain current (ID) characteristics for a gate length of 3 nm using Silvaco ATLAS 3D TCAD. In order to make a fair comparison between JL and IM In0.53Ga0.47As NT, the doping concentration of TM and QM JL In0.53Ga0.47As NT is tuned to achieve two specific objectives. Firstly, the goal is to produce the same ION as IM In0.53Ga0.47As NT. Secondly, the aim is to achieve the same threshold voltage (VTH) as IM In0.53Ga0.47As NT. It was discovered that the IOFF for JL devices is approximately 2.93 times smaller compared to IM devices in the TM situation, while considering matching ION and VTH. The JL devices have an IOFF that is 12.9 times smaller and an IOFF that is 102 times smaller compared to the IM device for the QM situation. This is achieved by matching the ION and VTH values. It achieves a lesser drain-induced barrier lowering (DIBL) of approximately 28.10 mV/V, a virtually perfect subthreshold slope (SS) of roughly 60mV/dec, and a larger current ratio of ION/IOFF, which is approximately 1.42 × 107.

Label-free biomolecule detection with dielectrically modulated double gate single cavity InGaAs/GaAsSb HTFET: Design considerations and performance evaluation

Dielectrically Modulated Double Gate Single Cavity InGaAs/GaAsSb HTFET (DMDG–SC–InGaAs/GaAsSb HTFET) is a novel label-free, nanocavity embedded dielectrically modulated heterostructure TFET-based biosensor. The III-V heterostructure (InGaAs/GaAsSb) has a high ION/IOFF ratio, better gate control, and higher tunnelling probability. In order to effectively reduce ambipolarity, asymmetrical doping is used at the p+ source and n+ drain, along with gate work function engineering. The stacked layers of HfO2/SiO2 gate oxide help to reduce the fringing electric field. The suggested device utilizes a dielectrically controlled technique to achieve biomolecule conjugation. This is done by etching a single nanogap cavity in the gate dielectric material towards the source end. An evaluation of the dielectric constants [K = 2.1, 2.63, 3.30, 6.3, and 12] of neutral and charged biomolecules compared to air [k = 1] is essential to determine the sensitivity of biosensors in an arid environment. The transconductance-to-current ratio (gm/Ids), switching ratio (ION/IOFF), and threshold voltage are the performance metrics used to evaluate the device sensitivity. The DM-DG–SC–InGaAs/GaAsSb HTFETpromises to be very sensitive while using less power during the detection process. It also shows that it could be a good choice for label-free biosensor applications.

Sensitivity enhancement using triple metal gate work function engineering of junctionless cylindrical gate all around SiNW MOSFET based biosensor for neutral biomolecule species detection for upcoming sub 14 nm technology node

In the present work Dielectric Modulation (DM) technique along with Triple Metal (TM) gate engineering has been used for the junctionless (JL) cylindrical gate all around (CGAA) Si nanowire (NW) MOSFET based biosensor for label free electrical detection of neutral biomolecules species like Uricase, Streptavidin, Protein, Biotin, ChOx (choline oxidase), and APTES etc. For this device, the Drift Diffusion approach has been used along with self-consistent solution of Schrodinger’s equation with Poisson’s equation. For the biomolecule immobilization, a nanogap cavity region is formed in the JL SiNW MOSFET by etching gate oxide layer above the SiO2 interfacial layer. The change in the drain current (ID), threshold voltage (Vth), off-current sensitivity (SIoff), threshold voltage sensitivity (SVth) and Ion/Ioff current ratio of the device have been considered as the sensing parameters for detection of biomolecules under dry environment condition. In present work a new sensing metric of sensing of biomolecules – DIBL has been added which has never been reported in literature. In this work for JL SiNW, sensitivity metrics like smaller DIBL ∼50.47 mV/V, higher SIoff9.33×105, higher SVth28.72, nearly ideal subthreshold slope (SS) ∼60 mV/dec, and higher Ion/Ioff current ratio ∼9.01 × 1012 have been obtained in comparison to available literature results.

Mole Fraction and Device Reliability Analysis of Vertical-Tunneling-Attributed Dual-Material Double-Gate Heterojunction-TFET with Si0.7Ge0.3 Source Region at Device and Circuit Level

This paper puts forward a new vertical-tunneling-attributed dual-material double-gate heterojunction-TFET (VTDMDG-HTFET). The device structure of VTDMDG-HTFET includes Si[Formula: see text]Ge[Formula: see text] material for the designing of source region. The mechanism of vertical tunneling in VTDMDG-HTFET provides superior electric field at tunneling interface and leads to improved transfer characteristics. VTDMDG-HTFET also includes metal gate work-function engineering approach to facilitate high ON-current and small OFF-current. Application of high-[Formula: see text] dielectric material HfO2 in the form of gate oxide enhances the capacitive-coupling at channel-source interface. Moreover, the work includes the comparison of proposed VTDMDG-HTFET with the conventional vertical-tunneling based dual-material double-gate-TFET (VTDMDG-TFET). It has been observed from the simulation results that SiGe source-based VTDMDG-HTFET offers better DC characteristics in terms of superior ON-current, smaller OFF-current, steeper subthreshold-slope, lower threshold voltage, higher transconductance along with smaller drain-induced barrier-lowering (DIBL) effects as compared to its counterpart silicon-source-based VTDMDG-TFET. In this work, reliability of VTDMDG-HTFET has also been examined and compared with VTDMDG-TFET in terms of temperature sensitivity and effect of different interface trap charges. The device simulation and investigations have been carried out using technology computer aided design (TCAD) tool. Moreover, device circuit mixed-mode simulation analysis is carried out for conventional and proposed device based resistive load inverters. A comparison is performed between both the inverters in terms of prorogation delay and switching threshold voltages. Further, the mixed mode simulation analysis is also performed for the proposed device based inverter under the influence of different interface trap charges (ITCs). Study shows that reliability performance of the proposed device is better as compared to its counterpart conventional device. Hence, vertical tunneling and SiGe source-based VTDMDG-HTFET can be a better choice for various applications such as analog/RF, analog and digital electronic circuits, energy harvesting, gas-sensing and memory devices.

A label-free dielectric-modulated biosensor using SiGe-heterojunction dual cavity dual metal electrically doped TFET

The detection of biomolecules has been accomplished in this article by using the tunnel field effect transistor’s (TFET) bipolar nature. The fabrication procedure has been made simpler, the prices have gone down, and random dopant fluctuation (RDFs) have been eliminated using the charge plasma concept. The objective of this work is to investigate the performance of a DopingLess- Dual Metal Gate- Dual Cavity- HeteroJunction- Tunnel Field Effect Transistor (DL-DMG-DC-HJ-TFET) biosensor that can sense biomolecules in both the ON and ambipolar states. It is feasible to recognize many types of biomolecules concurrently by taking into account the cavities at both tunneling junctions. The suggested biosensor’s OFF state current has been reduced and its sensitivity has been increased via the use of gate workfunction engineering and bandgap engineering. It has been investigated how the presence of proteins in the cavities affects electrical properties such as energy band diagram (EBD), surface potential (SP), subthreshold Swing (SS), threshold voltage , and current ratio The impact of temperature, germanium mole fraction, and position of biomolecules is also analyzed in this work. A comparative analysis for drain current sensitivity is presented considering different previous works.

Investigation of Si 1−X GeX source dual material stacked gate oxide pocket doped hetero-junction TFET for low power and RF applications

ABSTRACT In this paper, the applicability of dual material stacked gate-oxide-Pocket doped-hetero-junction tunnel field effect transistor (DMSGO-PD-HTFET) for low power switching and radio frequency (RF) applications is investigated. In this context, gate workfunction engineering, the stacked-gate-oxide (+) approach, and asymmetrical doping at the P+ source () and N+ drain regions are considered. N+ pocket at source-channel interface implements DMSGO-PD-HTFET and improves interband tunnelling rate. This research aims to improve the device’s switching ratio (/), average subthreshold swing (), and radio frequency (RF) performance. For this, the control gate work function, mole fraction (X), pocket thickness, and doping concentration are optimised. Next, the DC, analog/RF and linearity figure of merits of the proposed device is analysed and the performance is compared with conventional all-silicon dual-material stack gate oxide tunnel field effect transistor (DMSGO-TFET) and dual-material stacked gate oxide-hetero-junction tunnel field effect transistor (DMSGO-HTFET) with source using technology computer-aided design (TCAD) device simulator. Based on the comparative analysis, the optimised design with exhibits an average subthreshold swing () of 28.8 mV/decade, switching ratio (/) of 2 × 1012, cut-off frequency () of 216 (GHz), and other significant improvements in analog/RF and linearity performance parameters. The proposed device is therefore suitable for switching and RF applications.

Feasibility Study of Tuning the Threshold Voltage of Nanoscale Fin-shaped Field Effect Transistor (FinFET) via Metal Gate Workfunction Engineering

Feasibility Study of Tuning the Threshold Voltage of Nanoscale Fin-shaped Field Effect Transistor (FinFET) via Metal Gate Workfunction Engineering

Design and Investigation of Dielectrically Modulated Dual-Material Gate-Oxide-Stack Double-Gate TFET for Label-Free Detection of Biomolecules

This article investigates the applicability of dual-material gate-oxide-stack double-gate tunnel field effect transistor (DMGOSDG-TFET) as a biosensing element with the ability to assess the health parameters and disease onset. For this, employment of gate work-function engineering along with the gate-oxide-stack approach and asymmetrical doping at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}^{+}$ </tex-math></inline-formula> source and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}^{+}$ </tex-math></inline-formula> drain region are introduced for the first time to implement DMGOSDG-TFET-based biosensor. Also, a nanogap cavity is created by etching a portion of gate dielectric material toward the source end for the accomplishment of biomolecules conjugation in the proposed device. The main focus of this article is to estimate the underlying device sensitivity in the presence of different charged as well as neutral biomolecules. To explore such effects, different dielectric constants and negative charge densities of the biomolecules are considered independently in the nanogap cavity. Next, the sensing performance of the presented device is analyzed in terms of switching-ratio ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> ), transconductance-to-current ratio ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${g}_{m}/{I}_{ds}$ </tex-math></inline-formula> ), and average subthreshold-swing. A deep investigation of device performance is also performed with different fillings of the nanogap cavity and step-profiles arising out from the steric hindrance. The device sensitivity is analyzed for different cavity lengths and cavity thicknesses for the best outcomes. In addition, a comparative sensitivity analysis of DMGOSDG-TFET with single-material gate-oxide-stack double-gate tunnel field effect transistor (SMGOSDG-TFET) and metal–oxide–semiconductor field effect transistor (MOSFET)-based biosensor is also presented in this work. The device implementation and all the simulations are carried out using technology computer-aided design (TCAD) tool. All of the sensitivity-assessments disclose that DMGOSDG-TFET can be a good candidate for biosensing applications.

Design and Analysis of Dual-Metal-Gate Double-Cavity Charge-Plasma-TFET as a Label Free Biosensor

In this paper, the bipolar nature of tunnel field effect transistor (TFET) has been utilized for the first time for the identification of biomolecules. C harge plasma concept has been employed to achieve simpler process of fabrication, lower cost and to overcome random dopant fluctuation. The focus of this work is to utilize both ON and ambipolar state of dual metal gate double cavity charge plasma TFET (DMG-DC-CPTFET) biosensor for sensing the biomolecules. Consideration of cavities at both tunneling junctions, it is possible to sense different kinds of biomolecules simultaneously. Gate workfunction engineering has been employed to improve sensitivity and to minimize the OFF state current of the proposed biosensor. High-k gate dielectric is used to achieve maximum ON current. The variation in electrical characteristics like energy band, surface potential and the electric field resulting from the presence of charged and neutral biomolecules in the cavities has been studied. The proposed model offers maximum sensitivity of $2.88\times 10\,\,^{{11}}$ ( $2.88\times 10^{13}$ %) under ON state and $1.37\times 10^{{7}}$ ( $1.37\times 10^{9}$ %) under ambipolar state.

Explicit Threshold Voltage Modeling Insight for Short Channel Characterization of a WFE Elliptical GAA Strained-Si MOSFET

This paper presents explicit analytical modeling of a gate all around (GAA) strained silicon metal-oxide-semicondutor field-effect transistor (MOSFET) with elliptical cross section by incorporating the popular gate work function engineering (WFE) concept of lateral mole fraction variation from source to drain end. Surface potential and threshold voltage formulation of the proposed structure based on a quasi-three-dimensional scaling equation have been introduced. The derived model is further used to investigate the short channel characteristics of the device in terms of hot carrier effect (HCE), drain-induced barrier lowering (DIBL), threshold voltage roll off (TVRO), and subthreshold slope. The impact of device parameter variation including gate oxide thickness, effective radius, channel doping concentration, germanium (Ge) mole fraction variation in the strained silicon channel along with applied gate to source and drain biases are evaluated on device performance to justify its efficiency in comparison to its single gate material (SM) MOSFET equivalent. Our analytical analysis is further validated by ATLAS-3D device simulated data to verify the precision of the derived model.

Ambipolarity Suppressed Dual-Material Double-Source T-Shaped Tunnel Field-Effect Transistor

This article proposes a novel dual-material double-source T-shaped tunnel field-effect transistor (TFET) to suppress the ambipolar current conduction. The use of two sources in the proposed device doubles the tunneling junction area between the source and intrinsic regions, which consequently makes the TFET on-current double. To improve the switching ratio of the device, the gate work function engineering has been applied in the three-segmented gate structure of two different materials. The electrical characteristics of the investigated TFET with symmetric source-drain doping of 1 × 1020 cm−3 are studied using TCAD simulation. The simulation results demonstrate that the investigated device architecture with symmetric source-drain doping completely eliminates the ambipolar current when the applied bias voltage VGS is varied from 0 V to −1 V for VDS of 1 V. This TFET also exhibits a considerable improvement in the switching ratio.

Performance analysis of gate engineered dielectrically modulated TFET biosensors

ABSTRACT This paper presents, a short gate dual metal source electrode dielectrically modulated tunnel field-effect transistor (SDM SE DM-TFET) has been compared with conventional dual gate-source electrode dielectrically modulated tunnel field-effect transistor (DG SE DM-TFET) for the biosensing application. Hence, gate work function engineering is applied in our proposed device in which gate metal is split into two different work function segments as and . Additionally, a potential of −1.2 V is applied to the source electrode having a work function of . is the gate electrode work function at the source side and is the gate electrode work function at the drain side. The investigation is performed by varying the dielectric constant and charge density for choosing an optimised value for . The performance comparison has been done in terms of current, sensitivity and sensing speed. It can be verified from the simulated results that our proposed device exhibits superior performance as compared to the existing structures.

Performance optimization of a nanotube core–shell semi-junctionless p+p+n heterojunction tunnel field effect transistor

In this paper, the electrical characteristics of a heterojunction nanotube semi-junctionless tunnel field effect transistor (NSJTFET) with germanium in the source and GaAs in the drain channel regions are thoroughly investigated. The proposed n-channel NSJTFET is a p+p+n structure, employing internal core gate and external shell gate. The device under study provides a superior gate control over the channel by amplifying the band-to-band tunneling rate. The results imply that an increased on-state drive current of nearly 100 times as compared to the conventional nanowire tunnel field effect transistor (TFET) is achieved. In addition, the steep slope NSJTFET structure exhibits subthreshold swing of approximately 7.6 mV/dec in comparison with 25 mV/dec for the conventional TFET. Sensitivity analysis of main electrical parameters demonstrates that source-channel doping concentration and metal gate workfunction are critical design parameters that may affect the device performance. Moreover, a framework of core–shell gate workfunction engineering is utilized via calculating 2D variation matrix of the on-state current, threshold voltage and off-state current for optimizing the device performance.

Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to $\times 10$ ) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance.

Performance enhancement of core-shell JLFET by gate/dielectric engineering

ABSTRACTIn this paper, enhancement of volume depletion is studied on P-type double gate junctionless Field Effect Transistor (P-DGJLFET) by Gate work function and Gate dielectric engineering. The formation of parasitic BJT action in junctionless device along with DIBL effect is curtailed by integrating Rectangular Core-Shell (RCS) architecture with varying core doping along with different gate oxides and electrodes, respectively. After validating our simulations with the experimental results on Junctionless P-type FET, we demonstrated that RCS based P-DGJLFET with high K dielectric and aluminium as gate electrode exhibits superior ON/OFF ratio, Lower DIBL, better ON current, good OFF current and desired threshold voltage at channel length 5 nm. An exceptional ON/OFF current ratio (ION/IOFF) of 1010 is achieved when core is made thicker than shell. The DIBL is reduced by 62.5% when thin core along with SiO2 is replaced by thick core and HfO2. Also, the stringent requirement of lower work function in Junctionless P-type is relaxed using RCS architecture. The performance of RCS with polysilicon as gate electrode is better than conventional DGJLFET with aluminium as gate electrode. A comprehensive comparison on performances between different technology boosters applied on double gate JLT in the literature and proposed device is also presented.

Performance optimization of a nanoscale GaSb P-channel electron-hole bilayer tunnel field effect transistor using metal gate workfunction engineering

In this paper, the electrical characteristics of a double gate P-channel GaSb Electron-Hole Bilayer Tunnel Field Effect Transistor (EHBTFET) is comprehensively investigated and impact of main design parameters on the performance of the device is thoroughly assessed. The corresponding low carrier effective mass of GaSb provides high probability of tunneling current that eventually exhibits an improvement in the on-state current and subthreshold swing (SS). The results reveal that unlike the conventional tunnel field effect transistor (TFET) in which band to band tunneling current occurs horizontally from source to channel, the tunneling junction in EHBTFET is electrically created in the intrinsic channel in the entire region of the gate overlap length along the vertical direction. Due to the expanding of the tunneling area, the on-state current of EHBTEFT is increased five order of magnitude in comparison with lateral TFET and subthreshold swing of SS = 2 mV dec−1 with on/off current ratio of 2.5 × 1011 is achieved. The top and bottom gate workfunction are critical design parameters that fundamentally affect the tunneling rate. The 2D variation matrix of threshold voltage and on-state current are calculated as a function of top and bottom gate workfunction for optimizing the device performance. In addition, a comprehensive sensitivity analysis via calculating standard deviation and mean value of main electrical parameters are assessed to evaluate the susceptibility of device performance with respect to the variation of design parameters. The main feature of this device is the insensitivity of the tunneling rate to the source doping density that solves the problem of low solubility of dopants in III-V materials. Moreover, subthreshold swing and off-state current and are not affected by the gate length scaling, facilitating the employment of this device in nanoscale regime. The results in this paper pave the way for designing low power steep-slope logic circuits.

Performance investigation of steep-slope core–shell nanotube indium nitride electron–hole bilayer tunnel field effect transistor

In this paper, the effects of main physical and structural parameters on the electrical characteristics of indium nitride core–shell nanotube electron–hole bilayer tunnel field effect transistor (NEHBTFET) are comprehensively investigated via simulation study for optimizing the device performance. The proposed structure offers excellent band to band tunneling efficiency and steeper turn-on drain current by providing the tunneling junction normal to the gate electric field between the region of outer shell gate and inner core gate. The simulation results reveal that the on-state current and subthreshold swing of NEHBTFET are greatly improved via expanding the band to band tunneling area along the channel and in the vertical direction in comparison with conventional nanowire TFET with narrow lateral source–channel tunneling junction. The n+–p+ tunneling junction is created electrically in the intrinsic region and a framework of core and shell gate work function engineering are conducted via calculating 2D variation matrix of the on-state current and threshold voltage for optimizing the device performance. The sensitivity of device’s main electrical parameters with respect to the variation of device physical and geometrical parameters reveals that the electrical parameters are highly insensitive to the source doping density which solves the major challenge of low solubility of dopants in III-nitride devices. In addition, the off-state current and subthreshold swings are not affected by the gate length scaling that is an indication of feasibility of this device in nanoscale regime.

A novel design approach of charge plasma tunnel FET for radio frequency applications

In this paper, the impact of extra electron source (EES) and dual metal gate engineering on conventional charge plasma TFET (CP-TFET) have been done for improving DC and analog/RF parameters. CP-TFET structure is upgraded to double source CP-TFET (DS-CP-TFET) by placing an EES below the source/channel junction for enhancing the device performance in terms of driving current and RF figures of merit (FOMs). But, in spite of these pros, the approach is having cons of higher leakage current similar to MOSFET and negative conductance (inherent nature of TFET). Both the issues have been resolved in the double source dual gate CP-TFET (DS-DG-CP-TFET) by gate workfunction engineering and drain underlapping respectively. Additionally, for getting the optimum performance of DS-DG-CP-TFET, the device sensitivity has been investigated in terms of position of EES, length of drain electrode and workfunction of gate electrode 1 (GE1).

TFET performance optimization using gate work function engineering

This work presents main electrical characteristics improvement in a nanoscale tunnel field-effect transistor (TFET) with 50 nm channel length, applying work function engineering techniques. Three different metal gate materials with dedicated work functions are utilized to optimize the TFET performance. By gate work function and length optimization, the main parameters of Ion = 5×10−5 A/µm, Ioff = 2.5 × 10−15 A/µm, Iamb = 3×10−7 A/µm, and subthreshold swing = 51.01 mV/decade are obtained in accordance with tunneling barrier shape at source/channel and drain/channel tunnel junctions. The work function engineering techniques, presented in the current work, results in 1.22 times improvement in ION and 0.99 times improvement in IOFF.

Ambipolar SB-FinFETs: A New Path to Ultra-Compact Sub-10 nm Logic Circuits

Ultracompact sub-10-nm logic gates based on ambipolar characteristics of Schottky-barrier (SB) FinFETs and gate workfunction engineering (WFE) approach are introduced. Novel logic gate designs are proposed using WFE, whereby adjustment of workfunction in the contacts as well as two independently biased FinFET gates leads to an unprecedented degree of freedom for logic functionality that has not been explored before. The use of SB contacts, along with the high-k gate dielectric and ultrathin body, bestows a high-degree of short-channel immunity to the SB-FinFETs with ambipolar current–voltage characteristics down to 5 nm. The unique trait of the proposed novel logic gates is to lower CMOS transistor count by 50% and hence reduce overall area and power dissipation significantly. To illustrate this potential, an entirely novel conjugate (n/p channel) CMOS pass-gate transistor that can function as a two-transistor (2T) XOR and minimalist 2T NAND/NOR gates is designed and verified with TCAD simulations. Depending on the gate designed, TCAD simulations indicate that judicious choice of gate workfunctions between 3.7 and 5.2 eV can lead to CMOS logic gates with a power–delay product (PDP) at ${5}\times {10}^{-{18}}$ J level with immunity to ±0.1-eV workfunction variations. It is shown that WFE in independent-gate SB-FinFETs can lead to ultracompact logic circuits with 50% reduction in area and up to 10 times reduction in power, without significant degradation to overall PDP performance due to slower switching response compared with the conventional designs with p-n junction FinFET counterparts.