Performance optimization of a nanoscale GaSb P-channel electron-hole bilayer tunnel field effect transistor using metal gate workfunction engineering

Abstract

In this paper, the electrical characteristics of a double gate P-channel GaSb Electron-Hole Bilayer Tunnel Field Effect Transistor (EHBTFET) is comprehensively investigated and impact of main design parameters on the performance of the device is thoroughly assessed. The corresponding low carrier effective mass of GaSb provides high probability of tunneling current that eventually exhibits an improvement in the on-state current and subthreshold swing (SS). The results reveal that unlike the conventional tunnel field effect transistor (TFET) in which band to band tunneling current occurs horizontally from source to channel, the tunneling junction in EHBTFET is electrically created in the intrinsic channel in the entire region of the gate overlap length along the vertical direction. Due to the expanding of the tunneling area, the on-state current of EHBTEFT is increased five order of magnitude in comparison with lateral TFET and subthreshold swing of SS = 2 mV dec−1 with on/off current ratio of 2.5 × 1011 is achieved. The top and bottom gate workfunction are critical design parameters that fundamentally affect the tunneling rate. The 2D variation matrix of threshold voltage and on-state current are calculated as a function of top and bottom gate workfunction for optimizing the device performance. In addition, a comprehensive sensitivity analysis via calculating standard deviation and mean value of main electrical parameters are assessed to evaluate the susceptibility of device performance with respect to the variation of design parameters. The main feature of this device is the insensitivity of the tunneling rate to the source doping density that solves the problem of low solubility of dopants in III-V materials. Moreover, subthreshold swing and off-state current and are not affected by the gate length scaling, facilitating the employment of this device in nanoscale regime. The results in this paper pave the way for designing low power steep-slope logic circuits.