Gate Work Function Engineering Research Articles

New dual material double gate junctionless tunnel FET: Subthreshold modeling and simulation

A subthreshold analytical model for Dual Material Double Gate Junctionless Tunnel FET (DMDG JLTFET) is developed. To analyze the behavior of short channel device, relevant parameters such as surface potential, electric field, threshold voltage, drain current, transconductance-to-drain current ratio, subthreshold slope and subthreshold swing are extracted from the 2-D analytical solution of Poisson's equation. Relating DMDG JLTFET to Junctionless MOSFETs, the results show significant reduction of Short Channel Effects (SCEs) at the drain end. The analytical model for DMDG JLTFET is effective due to the combined supremacy of uniform doping in the channel, usage of high-K gate dielectric material and work function engineering in the gate metal. The results obtained from the analytical model are simulated and validated using 2-D Sentaurus TCAD device simulator.

Performance evaluation of normally ON/OFF junctionless vertical channel GaN FET

GaN vertical channel junction field-effect transistor (VC-JFET) is a relatively new technology, which is particularly suitable for high-power applications. In these devices, the channel is formed between two p-GaN current blocking layers which is a complex and costly process. In addition, various traps and defects get introduced during the fabrication of p-GaN layers. The traps and defects near the interface of the p-GaN layer and n-GaN channel can deteriorate the device performance. Therefore, for reducing the fabrication complexity with enhanced device performance, a normally ON/OFF GaN vertical channel junctionless field-effect transistor (VC-JLFET) is proposed in this paper. The results are compared against conventional GaN VC-junction field-effect transistor (VC-JFET) of the equal dimensions and doping concentrations. The absence of p–n junction at source and drain in the proposed device offers less fabrication complexity, cost, and thermal budget as compared to the referenced device. The proposed device provides more than four times drain current ( $$8.37\times 10^{-6}$$ A/μm) as compared to the referenced device ( $$1.9 \times 10^{-6}$$ A/μm) at similar physical and bias conditions. The obtained values of ON resistance, trans-conductance, unity gain bandwidth frequency, and breakdown voltage for the proposed normally ON device (at Lap = 0.9 μm, Vth = −3.5 V, VG = −1V, VD = 1 V) are 5.63 × 103 Ω/μm, 6.99 × 10−7 S/μm, 1.56 × 108 Hz and 700 V, respectively. While in normally OFF mode, the obtained values of parameters such as threshold voltage, ON resistance, breakdown voltage, and drain current are 2 V, $$1.56 \times 10^{6}$$ Ω/μm, greater than 1000 V and $$1.54 \times 10^{-6}$$ A/μm, respectively. The normally OFF VC-JLFET is achieved by gate work-function engineering in conjunction with doping optimization.

Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high-k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

Performance Assessment of A Novel Vertical Dielectrically Modulated TFET-Based Biosensor

A vertical dielectrically modulated tunnel field-effect transistor (V-DMTFET) as a label-free biosensor has been investigated in this paper for the first time and compared with lateral DMTFET (L-DMTFET) using underlap concept and gate work function engineering. To improve the performance of lateral biosensor (LB), a heavily doped front gate ${n}^{+}$ -pocket and gate-to-source overlap is introduced in the vertical biosensor (VB). The integrated effect of lateral tunneling as well as vertical tunneling in VB leads to enhanced ON-state current and decrease the subthreshold swing. To evaluate sensing ability of these devices, charged and charged neutral biomolecules are immobilized in nanogap cavity independently. A deep analysis has been performed to show the effect of variation in dielectric constant ( $k$ ), charge density ( $\rho $ ), ${x}$ -composition of Ge, % volume filling of ${t}_{\textsf {cavity}}$ , length and thickness of a ${n}^{+}$ -pocket and sensitivity of electrical parameters is also incorporated. Dual-pocket (front and back gate pocket) VB is studied and compared with the LB and VB in the tabular form. Noise characteristic of dielectrically modulated field-effect transistor, L-DMTFET, and V-DMTFET is also evaluated.

A Comparative Numerical Study of Junctionless and p-i-n Tunneling Carbon Nanotube Field Effect Transistor

In this paper, a gate-all-around junctionless tunnel field effect transistor (JL-TFET) based on carbon nanotube (CNT) material is introduced and simulated. The JL-TFET is a CNT-channel heavily n-type-doped junctionless field effect transistor (JLFET) which utilizes two insulated gates (Control-Gate, P-Gate) with two different metal workfunctions in order to treat like tunnel field effect transistor (TFET). In this design, the privileges of JLTFET and TFET are mixed together. The numerical comparative study on the performance characteristics of JL-TFET and conventional p-i-n TFET demonstrated that the proposed JL-TFET has a higher ON-state current driveability (ION), a larger ON/OFF-current ratio (ION/IOFF), a lower drain induced barrier lowering (DIBL), a shorter delay time (τ), and also a superior cut-off frequency (ƒT). Moreover, in order to further performance improvement of proposed JLTFET, three novel device structures namely as junctionless linear descending gate workfunction TFET (JL-LDWTFET), junctionless linear ascending gate workfunction TFET (JL-LAWTFET) and junctionless triple metal gate TFET (JL-TMGTFET) are proposed by gate workfunction engineering approach. According to simulation results, the JL-TMGTFET with the gate composed of three segments of different work functions shows excellent characteristics with high ION/IOFF ratio, a superior ambipolar characteristic, a shorter delay time and a better cut-off frequency compared to conventional p-i-n TFET and other proposed junctionless-based features. All the simulations are done with the full quantum mechanical simulator for a channel length of 60-nm using nonequilibrium Green’s function (NEGF) method.

A Numerical Study on Graphene Nanoribbon Heterojunction Dual-Material Gate Tunnel FET

In this letter, a tunnel FET (TFET) combining both graphene nanoribbon (GNR) heterojunction (HJ) and gate work function (WF) engineering is studied with the numerical simulation. The lowest subthreshold swing is smaller than 15 mV/decade and the ON state current ( $I_{{\mathrm{\scriptscriptstyle ON}}}$ ) reaches to $1.7~\mu \text{A}$ with device width smaller than 3 nm. The tunnel width is well reduced with the dual-material gate (DMG) structure boosting the ON current. The channel with a wide energy gap ( $E_{g}$ ) GNR can effectively reduce the leakage current at OFF state when its length is 13 nm. It is found out that large WF difference between the gate and the GNR not only effectively enhances the tunneling effect but also leads to an electron quantum well hindering the regulation capability of the gate. This effect can be well reduced with large WF gate material on the top of the HJ region. The numerical simulation reveals that the GNR HJ-DMG TFET is a good candidate for low power applications.

A novel gate and drain engineered charge plasma tunnel field-effect transistor for low sub-threshold swing and ambipolar nature

In this paper, we focus on the improvement of figures of merit for charge plasma based tunnel field-effect transistor (TFET) in terms of ON-state current, threshold voltage, sub-threshold swing, ambipolar nature, and gate to drain capacitance which provides better channel controlling of the device with improved high frequency response at ultra-low supply voltages. Regarding this, we simultaneously employ work function engineering on the drain and gate electrode of the charge plasma TFET. The use of gate work function engineering modulates the barrier on the source/channel interface leads to improvement in the ON-state current, threshold voltage, and sub-threshold swing. Apart from this, for the first time use of work function engineering on the drain electrode increases the tunneling barrier for the flow of holes on the drain/channel interface, it results into suppression of ambipolar behavior. The lowering of gate to drain capacitance therefore enhanced high frequency parameters. Whereas, the presence of dual work functionality at the gate electrode and over the drain region improves the overall performance of the charge plasma based TFET.

A Novel PNIN Barrier Controlled Tunnel FET

A novel structure of barrier controlled tunnel FET is proposed in the paper. The principles of gate work function engineering and channel doping engineering are combined to form up an in channel potential barrier, which can tune the source to drain tunnel current. The proposed structure serves as an alternative solution of barrier controlled tunnel FET fabrication, which combines the merits of the barrier controlled traditional MOSFET device and the bandgap controlled tunnel device. With carbon nanotube as the channel material, the device performance of the novel structure is verified using numerical simulation under the non-equilibrium Green’s function framework.

Binary alloy enabled gate work function engineering of nanoscale UTB-GeOI MOSFETs for mixed-signal system-on-chip applications

We report the impact of different work function profiles of the gate material on the analog and logic performance of ultra-thin body GeOI MOSFETs at channel length of 30nm based on extensive numerical device simulations. Five such profiles with the work function in the range 4.16–5.05eV are obtained by varying the composition of the binary alloy Ta–Pt. Various device parameters related to analog circuits such as transconductance, transconductance efficiency, output conductance, intrinsic gain and unity-gain cut-off frequency are systematically obtained for devices having different work function profiles. Also evaluated is the logic performance of the device from the delay versus ION/IOFF and IOFF data plots. Our investigations reveal that the output conductance and gain outperform for devices with an increasingly graded work function from the source to the drain while the device with a constant work function yields improved transconductance, transconductance efficiency, unity gain cut-off frequency, and delay.

Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied–independent gate and symmetric–asymmetric options

Novel analytical models for subthreshold current and subthreshold slope of a generic underlap DGMOSFET are proposed. The proposed models are validated with published models, experimental data along with numerical simulation results. The reasonably good agreement shows the accuracy of the proposed model. It is demonstrated how device subthreshold leakage current and subthreshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering. It is demonstrated that independent gate operation in combination with gate underlap engineering significantly reduce subthreshold leakage currents as compared to nonunderlap-tied gate DGMOSFET. With the reduction in body thickness, an improvement in subthreshold slope value of underlap 4T DGMOSFET is seen, particularly as back/front gate oxide asymmetry. Developed models demonstrate that asymmetric work function underlap 4T DGMOSFETs would have better device subthreshold slope value along with increased back gate oxide asymmetry.

Performance improvement in narrow MuGFETs by gate work function and source/drain implant engineering

At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short channel effect (SCE) control than their bulk Si counterpart [Doyle BS et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev Lett 2003;24(4):263–5, van Dal MJH et al. Highly manufacturable FinFETs with sub-10 nm fin width and high aspect ratio fabricated with immersion lithography. In: VLSI Symp Tech Dig; 2007. p. 110–1 [1,2]]. In addition, their undoped channels allow a substantial reduction of the threshold voltage ( V T) mismatch, which makes the MuGFET an excellent candidate for replacing planar MOSFETs in SRAM structures. However, as the Si fin width ( W fin) and gate length ( L g) are down-scaled in order to improve the SCE control and current drive, respectively, the gate work function and access resistance ( R SD) engineering become more challenging. In this paper, two approaches for optimizing the performance of narrow MuGFETs are reported and analysed: the first one relies on the thickness of their Plasma-Enhanced-ALD (PE-ALD) TiN gate electrode. It is demonstrated that very thin PE-ALD TiN gate electrodes allow improved SCE control and enhanced performance in nMOS MuGFETs. The second approach relies on non-amorphizing ion (boron) implantations for both extension and HDD implantations. A substantial R SD reduction is demonstrated for pMOS MuGFETs with Si fin widths down to 10 nm.

Work Function Engineering Within a Single Metal Gate Stack: Manipulating Terbium- and Aluminum-Induced Interface Dipoles of Opposing Polarity

In this paper, a systematic study on combining n-type and p-type interface dipoles for metal gate work function (Phi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) engineering within the same gate stack was conducted. Ultrathin terbium (Tb) and aluminum (Al)-based interlayers (ILs) were utilized for n- and p-type dipole formation, respectively, to modulate the net interface dipole magnitude and polarity within a metal gate stack. By controlling the net interface dipole through Tb- and Al-based ILs, continuous TaN Phi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> tunability of ~ 0.7-0.8 eV (after either a 500degC or 950degC anneal) on SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric was attained. The reversal of net interface dipole polarity was demonstrated using both TaN/SiO2 and TaN/high-kappa gate stacks by varying IL metal species and anneal conditions. A convenient way in reversing a Tb-induced (n-type) dipole through Al-incorporation via the TaN metal gate using a ldquogate-firstrdquo process is also shown. The dominant dipole that results in the metal gate stack hinges critically on the reactions of Al and Tb with SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (or underlying SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> for high-kappa stacks) for Al-O-(Si) and Tb-O-Si bond formation, respectively. This concept of manipulating interface dipoles of opposing polarity for metal gate Phi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> tunability could open up new avenues for achieving multiple Phi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> using a single metal gate and a simple integration scheme.

Two Dimensional Analytical Potential Modeling of Nanoscale Fully Depleted Metal Gate Double Gate MOSFET

In this paper, a 2D analytical potential modeling of nanoscale Double Gate MOSFET is carried out through evaluation of center and surface potential. An analytical expression of 2D potential for asymmetric double gate MOSFET and symmetric double gate MOSFET with ultra thin body (UTB) with the consideration of boundary value approach problem based on the physics of the device has been developed. The center and surface potential model is developed analytically in this paper which is valid below threshold voltage. The post threshold characteristics has been done using ATLAS simulator. Further, in this paper with the proper gate workfunction engineering, we have modeled the 2D potential for midgap semiconductor with workfunction of gate material as 4.61 eV and for Metal Gate Double Gate MOSFET, Hf as a gate metal with buffer layer AIN x with the workfunction of the gate material as 4.4 eV. Quantum corrections are applied for potential modeling as well as threshold voltage modeling. Further, the variation of gate to gate and source to drain potential is carried out. For the purpose of verification and validation of our proposed model, we have compared and contrasted the results obtained through our model and the results obtained through 2D ATLAS device simulator. A close match is obtained between the two, thus validating the approach followed is our analytical model.

Device-Aware Yield-Centric Dual-$V_{t}$ Design Under Parameter Variations in Nanoscale Technologies

Dual-Vt design technique has proven to be extremely effective in reducing subthreshold leakage in both active and standby mode of operation of a circuit in submicrometer technologies. However, aggressive scaling of technology results in different leakage components (subthreshold, gate and junction tunneling) to become significant portion of total power dissipation in CMOS circuits. High-Vt devices are expected to have high junction tunneling current (due to stronger halo doping) compared to low-Vt devices, which in the worst case can increase the total leakage in dual-Vt design. Moreover, process parameter variations (and in turn Vt variations) are expected to be significantly high in sub-50-nm technology regime, which can severely affect the yield. In this paper, we propose a device aware simultaneous sizing and dual-Vt design methodology that considers each component of leakage and the impact of process variation (on both delay and leakage power) to minimize the total leakage while ensuring a target yield. Our results show that conventional dual-Vt design can overestimate leakage savings by 36% while incurring 17% average yield loss in 50-nm predictive technology. The proposed scheme results in 10%-20% extra leakage power savings compared to conventional dual-Vt design, while ensuring target yield. This paper also shows that nonscalability of the present way of realizing high-Vt devices results in negligible power savings beyond 25-nm technology. Hence, different dual-Vt process options, such as metal gate work function engineering, are required to realize high-performance and low-leakage dual-Vt designs in future technologies.

Physics and Integration of Fully-Depleted Silicon-On-Insulator Devices

This paper gives an overview of the device physics and the process integration challenges of fully-depleted (FD) silicon-on-insulator (SOI) devices for advanced technology nodes. In the first part of the presentation, the physics related to the operation of ultra-thin film devices is described as well as how device scaling is impacted by the device parameters. Next, major fabrication challenges faced by fully-depleted SOI devices are reviewed along with their most recent progress. The technology modules reviewed include isolation, substrate engineering (limits of ultra-thin layers, strained layers, buried insulator materials,...), gate stack (high k and gate workfunction engineering techniques), methods for reducing SD parasitic resistance, such as elevated source/drain, as well as stress techniques.

Impact of High-$k$ Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs

The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">of</sub> in addition to an increase in the internal fringe capacitance C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">if</sub> with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering

Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering

This paper shows that the Surrounding Gate Transistor (SGT) can be scaled down to decananometer gate lengths by using an intrinsically-doped body and gate work function engineering. Strong gate controllability is an essential characteristics of the SGT. However, by using an intrinsically-doped body, the SGT can realize a higher carrier mobility and stronger gate controllability of the silicon body. Then, in order to adjust the threshold voltage, it is necessary to adopt gate work function engineering in which a metal or metal silicide gate is used. Using a three-dimensional (3D) device simulator, we analyze the short-channel effects and current characteristics of the SGT. We compare the device characteristics of the SGT to those of the Tri-gate transistor and Double-Gate (DG) MOSFET. When the silicon pillar diameter (or silicon body thickness) is 10nm, the gate length is 20nm, and the oxide thickness is 1 nm, the SGT shows a subthreshold swing of 63 mV/dec and a DIBL of -17 mV, whereas the Tri-gate transistor and the DG MOSFET show a subthreshold swing of 71 mV/dec and 77 mV/dec, respectively, and a DIBL of -47 mV and -75 mV, respectively. By adjusting the value of the gate work function, we define the off current at V G = 0 V and V D = 1V. When the off current is set at 1 pA/μm, the SGT can realize a high on current of 1020μA/μm at V G = 1V and V D = V. Moreover, the on current of the SGT is 21% larger than that of the Tri-gate transistor and 52% larger than that of the DG MOSFET. Therefore, the SGT can be scaled reliably toward the decananometer gate length for high-speed and low-power ULSI.

Scaling the Vertical Tunnel FET With Tunnel Bandgap Modulation and Gate Workfunction Engineering

In this paper, we look into the scaling issues of a vertical tunnel field-effect transistor (FET). The device, a gated p-i-n diode based on silicon, showed gate-controlled band-to-band tunneling from the heavily doped source to the intrinsic channel. An exponentially increasing input characteristics, perfect saturation in the output characteristics, and off-currents of the order of 1 fA//spl mu/m for sub-100-nm channel lengths were observed. Further, with a /spl delta/p/sup +/ SiGe layer at the p-source end, improvements in the device performance in terms of on-current, threshold voltage and subthreshold swing were shown, albeit trading off the off-currents which increase with Ge content x. We show here that the tunnel FET performance is nearly independent of channel length scaling L and with /spl delta/p/sup +/ SiGe layer, scaling t/sub ox/ is not critical to tunnel FET scaling. Further, with gate workfunction engineering, the tunnel FET can be tuned to achieve a high on-current as well as very low off-currents. Due to the perfect saturation in the output characteristics, the device looks good for sub-100-nm low-power analog devices.

Fabrication and characterization of vertical-type, self-aligned asymmetric double-gate metal-oxide-semiconductor field-effect-transistors

For gate work function engineering required for ultrathin channel (UTC) double-gate (DG) metal-oxide-semiconductor field-effect-transistor (MOSFET), threshold voltage (Vth) tuning of self-aligned asymmetric (n+–p+) DG MOSFETs have been experimentally investigated in comparison with symmetric (n+–n+) DG MOSFETs. The vertical UTCs (12–32nm) were fabricated on bulk Si substrates by utilizing the novel ion-bombardment-retarded wet etching and the self-aligned asymmetric DGs were formed by employing the tilted ion implantation and anisotropic dry etching. The fabricated vertical asymmetric DG n-MOSFET with the gate length of 100nm clearly exhibits the desirable Vth of +0.1V, in addition to the unique DG MOSFET characteristics of the high short-channel-effect immunity with decreasing a channel thickness.

A Device Design Methodology for Sub-100-nm SOC Applications Using Bulk and SOI MOSFETs

CMOS for the mixed-mode applications has gained much interest recently. While the International Technology Roadmap for Semiconductors provides two different scaling guidelines for the analog and digital circuit operation using the bulk MOSFET, there are no well-defined scaling guidelines for improving the analog performance of silicon-on-insulator (SOI) MOSFETs. This paper presents a systematic and quantitative comparison between the analog characteristics of the bulk and SOI technology. The intrinsic gain, f/sub T/ and g/sub m//I/sub ds/ ratio are considered as a metric for this comparison. It is shown that, even for the operating frequencies in the range of gigahertz (where the ac kink effect is suppressed), analog performance of SOI devices is inferior to that of the bulk devices due to the capacitive drain-to-body coupling. Based on our study, we show that hat the gate-workfunction engineering (close to mid-gap workfunction) is essential in fully depleted SOI (FDSOI) devices for improving analog performance. The analog performance of partially depleted SOI (PDSOI) devices can be improved by using body-tied structures. An increased gate control in double-gate MOSFETs can provide very high output resistance for short-channel devices.