Gate Work Function Engineering Research Articles

Low-frequency noise characteristics of ultrathin body p-MOSFETs with molybdenum gate

We report the low-frequency noise characteristics of ultrathin body (UTB) p-channel MOSFETs with molybdenum (Mo) as the gate material. Using the number fluctuation model with correlated mobility fluctuation, the dependence of the noise behavior on bias condition is explained. The impact of nitrogen implantation (for gate work function engineering) on the noise behavior is also presented. An exponential increase in noise with nitrogen implant dose is attributed to interface-trap generation caused by nitrogen penetration through the gate oxide.

Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology

The dependence of the metal gate work function on the underlying gate dielectric in advanced metal-oxide-semiconductor (MOS) gate stacks was explored. Metal work functions on high-κ dielectrics are observed to differ appreciably from their values on SiO2 or in vacuum. We applied the interface dipole theory to the interface between the gate and the gate dielectric of a MOS transistor and obtained excellent agreement with experimental data. Important parameters such as the slope parameters for gate dielectrics like SiO2, Al2O3, Si3N4, ZrO2, and HfO2 were extracted. In addition, we also explain the weaker dependence of n+ and p+ polysilicon gate work functions on the gate dielectric material. Challenges for gate work function engineering are highlighted. This work provides additional guidelines on the choice of gate materials for future MOS technology incorporating high-κ gate dielectrics.

Effects of high-/spl kappa/ gate dielectric materials on metal and silicon gate workfunctions

The dependence of metal and polysilicon gate work-functions on the underlying gate dielectric in advanced MOS gate stacks is explored. We observe that the metal workfunctions on high-/spl kappa/ dielectrics differ appreciably from their values on SiO/sub 2/ or in a vacuum. We also show the first application of the interface dipole theory on the metal-dielectric interface and obtained excellent agreement with experimental data. Important parameters such as the slope parameters for SiO/sub 2/, Si/sub 3/N/sub 4/, ZrO/sub 2/, and HfO/sub 2/ are extracted. In addition, we also explain the weaker dependence of n+ and p+ polysilicon gate workfunctions on the gate dielectric. Challenges for gate workfunction engineering are highlighted. This work provides additional guidelines on the choice of gate materials for future CMOS technology incorporating high-/spl kappa/ gate dielectrics.

A 0.13 μm poly-SiGe gate CMOS technology for low-voltage mixed-signal applications

We present here a novel approach to CMOS fabrication based on advanced lateral channel doping profiling technique coupled to gate workfunction engineering. The performance of this technology for both digital and analog applications is evaluated in detail to illustrate that it satisfies the requirements for mixed digital-analog circuitry. The use of asymmetric source/drain lateral profiles proves to be especially beneficial to analog applications.

Polycrystalline silicon/metal stacked gate for threshold voltage control in metal–oxide–semiconductor field-effect transistors

A stack structure for the gate electrode of metal–oxide–semiconductor (MOS) transistors is proposed, analyzed, and simulated. The stack consists of a very thin polycrystalline silicon (polysilicon) layer and metal. By changing the thickness of the polysilicon layer, one can change the effective work function of the gate. Thus, the stacked-gate structure allows for a method to continuously adjust MOS field-effect transistor threshold voltage through gate work-function engineering while retaining the proven SiO2/polysilicon interface.

Advanced technologies for optimized sub-quarter-micrometer SOI CMOS devices

Two manufacturable technologies of fully-depleted (FD) thin-film silicon-on-insulator (SOI) MOSFET's for low-power applications are proposed in this paper. To maintain high current drive while aggressively thinning down the SOI film, silicide is to be formed on Ge-damaged silicon layers. Ge preamorphization facilitates silicide formation at low temperature (/spl sim/450/spl deg/C) and effectively controls the silicide depth without void formation. It also reduces the floating body effect. In addition, a reliable gate work-function engineering is introduced for good threshold voltage management. A p/sup +/SiGe/Si stack gate alleviates the threshold voltage instability of SOI due to film thickness nonuniformity and broadens the design window for channel doping. These advanced technologies, compatible with existing bulk CMOS technology, are integrated into SOI CMOS process. Excellent electrical device results are presented.

TRACE—traceability and reliability assuring computerized environment : Koji Ohtoriet al. Proceedings of the 21st Symposium on Reliability and Maintainability, Japan, 25 (June 1991)

At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short channel effect (SCE) control than their bulk Si counterpart [Doyle BS et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev Lett 2003;24(4):263–5, van Dal MJH et al. Highly manufacturable FinFETs with sub-10 nm fin width and high aspect ratio fabricated with immersion lithography. In: VLSI Symp Tech Dig; 2007. p. 110–1 [1], [2]]. In addition, their undoped channels allow a substantial reduction of the threshold voltage (VT) mismatch, which makes the MuGFET an excellent candidate for replacing planar MOSFETs in SRAM structures. However, as the Si fin width (Wfin) and gate length (Lg) are down-scaled in order to improve the SCE control and current drive, respectively, the gate work function and access resistance (RSD) engineering become more challenging.In this paper, two approaches for optimizing the performance of narrow MuGFETs are reported and analysed: the first one relies on the thickness of their Plasma-Enhanced-ALD (PE-ALD) TiN gate electrode. It is demonstrated that very thin PE-ALD TiN gate electrodes allow improved SCE control and enhanced performance in nMOS MuGFETs. The second approach relies on non-amorphizing ion (boron) implantations for both extension and HDD implantations. A substantial RSD reduction is demonstrated for pMOS MuGFETs with Si fin widths down to 10 nm.