Gate Switching Research Articles

Quantum ATK analysis of silicon nanowire FET with a cylindrical metallic wrap-around gate varied with dielectrics

The nanowire FET is a game-changing technology because the gate is wrapped around the channel, allowing for greater applications for gate controllability and switching. The usage of dielectrics with the Nanowire Field Effect Transistor is discussed in this work. The device is investigated for three different dielectric constants using quantum ATK software. For each dielectric, sub-threshold conditions such as Drain induced barrier lowering, subthreshold slope, I ON and I OFF currents are investigated. For dielectric 4,9,25, the I ON /I OFF ratio was found to be 0.86 × 10 7 , 0.22 × 10 7 & 0.12 x10 7 for the described devices, respectively. The subthreshold slope for the same three dielectrics was calculated as 298.416 mV/dec, 285.8914 mV/dec & 190.66 mV/dec. Subthreshold conditions can be suppressed using the gate and drain control parameters. Many further evaluations are carried out to determine how we can employ the designed device for sensor applications.

Crosstalk Induced Shoot-Through in BTI-Stressed Symmetrical & Asymmetrical Double-Trench SiC Power MOSFETs

In this paper, the crosstalk-induced shoot-through current and induced gate voltage of SiC planar MOSFETs, SiC symmetrical double-trench MOSFETs and SiC asymmetrical double-trench MOSFETs is investigated on a half-bridge circuit to analyse the impact of temperature, drain-source voltage switching rate, gate resistance and load current level on crosstalk-induced properties of different SiC MOSFET structures. It shows that due to the smaller gate-source capacitance, the two double-trench MOSFETs exhibit higher induced gate voltage during crosstalk with the same external gate resistance, which together with the higher transconductance, yield higher shoot-through current than the planar MOSFET. Accordingly, their shoot-through current decreases with increasing of the load current while the planar MOSFET exhibits an opposite trend. The different trend of shoot-through current with temperature on DUTs reveals that the crosstalk in different device structures are dominated by different mechanisms, i.e. threshold voltage and channel mobility with the gate-source capacitance influencing the amplitude. Impact of bias temperature instability with positive and negative gate stressing is measured with a range of stress and recover periods at temperateness ranging between 25 °C to 175 °C. These measurements show that the peak shoot-through correlates with the threshold drift, though with less sensitivity for SiC symmetrical and asymmetrical double-trench MOSFETs compared with the planar SiC MOSFET where the inter-dependence is pronounced. A model is developed for the induced gate voltage and shoot-through current during crosstalk with channel current considered. The comparison of the model results with measurement confirms its capability to predict crosstalk in different MOSFET structures.

Study of Current Collapse Behaviors of Dual-Gate AlGaN/GaN HEMTs on Si

Surface traps on GaN-based HEMTs (high-electron-mobility transistors) usually result in the increase of channel on-resistance. It becomes worsen when short pulses are applied during high-frequency and high voltage switching. Here we present a dual-gate transistor structure to suppress the dynamic on-resistance increase. The auxiliary gate under a proper fixed voltage is able to induce additional electrons to compensate the channel carrier loss during main gate switching, leading to a lower dynamic on-resistance. In this work, we benchmarked the fundamental electrical properties of both single-gate and dual-gate HEMTs. We further extracted the dynamic electrical properties by stressing the devices with short pulses. The results suggest a significant mitigation of current collapse of a dual-gate HEMT under a proper bias applied on the auxiliary gate electrode. The physical mechanism based on the charge distribution in the channel is employed to explain the observations.

A High-Efficiency Triple-Mode Active Rectifier With Gate Charge Recycling Technique for Wireless Power Transfer System

This paper presents an active rectifier design with a gate charge recycling technique. Gate switching increases the switching losses of the active rectifier, therefore, as a way to reduce switching losses, the gate charge recycling technique is proposed. The output power of 15 W is achieved to enable rapid charging using the three standards for wireless charging mode, magnetic induction (WPC and PMA), and magnetic resonance (A4WP). Power-sharing is used to lower the amount of power consumed by each standard mode core. In WPC, and PMA mode zero current sensing (ZCS) technique has been used while in the A4WP mode, the digitally controlled delay adjustment (DCDA) technique has been employed. By using a gate charge recycling block, the efficiency has been considerably improved due to the lower power consumption. It aims to increase the overall efficiency by reusing switching loss using the gate charge recycling block, and it has effectiveness by allowing three standard modes to operate with one single chip. The proposed design combines charge-recycling with zero current sensing techniques to improve power efficiency. The layout size is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.75~\mu \text{m}^{2}$ </tex-math></inline-formula> . The achieved efficiency is 98.6 % in the magnetic induction method (WPC/PMA) at 15 W, and 94.86 % in the magnetic resonance method (A4WP) with an output power level of 15 W. The chip is fabricated in the BCD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS process.

Dynamic Surface Layer Coiled Coil Proteins Processing Analog-to-Digital Information.

Surface layer proteins perform multiple functions in prokaryotic cells, including cellular defense, cell-shape maintenance, and regulation of import and export of materials. However, mimicking the complex and dynamic behavior of such two-dimensional biochemical systems is challenging, and hence research has so far focused mainly on the design and manipulation of the structure and functionality of protein assemblies in solution. Motivated by the new opportunities that dynamic surface layer proteins may offer for modern technology, we herein demonstrate that immobilization of coiled coil proteins onto an inorganic surface facilitates complex behavior, manifested by reversible chemical reactions that can be rapidly monitored as digital surface readouts. Using multiple chemical triggers as inputs and several surface characteristics as outputs, we can realize reversible switching and logic gate operations that are read in parallel. Moreover, using the same coiled coil protein monolayers for derivatization of nanopores drilled into silicon nitride membranes facilitates control over ion and mass transport through the pores, thereby expanding the applicability of the dynamic coiled coil system for contemporary stochastic biosensing applications.

Stigmergic electronic gates and networks

Stigmergy is a communication method based on changing the surrounding environment according to reference feedbacks. It is typical within animal colonies that are able to process even complex information by releasing signals into the environment, which are subsequently received and processed by other elements of the colony. For example, ants searching for food leave traces of a pheromone, like Hansel and Gretel’s breadcrumbs, along the way. When food is found, they return to the anthill reinforcing this pheromone trace as a signal and reminder to all the others. Similar techniques are used in routing software even if stigmergic hardware might be even more efficient, fast, and energy saving. Recently, a stigmergic photonic gate based on soliton waveguides has been proposed; this particular stigmergic hardware can switch the output ratio of the channels as a result of optical feedback. Based on these results, in this study, we analyze stigmergic electronic gates that can be addressed through external feedback, as the photonic ones do. We show that the nonlinear response of such gates must be based on quadratic saturating conductances driven by feedback signals. For this purpose, networks of stigmergic gates require two parallel and communicating current circuits: one to transmit information, and another for feedback signals to control the gate switching. We also show that by increasing the number of terminals per single gate, from 2 × 2 to 3 × 3 or higher, the overall power consumption can be reduced by a few orders of magnitude.

A Design of a Robust Analog PWM Solar Charge Controller for the Off-Grid Solar Home System: Fixed Frequency Current Control Mode

Solar Home System (SHS) is a stand-alone power solution in an isolated area where the national power grid connection is not accessible. Presently using the off-grid solar home system has one solar panel, one lead-acid batter, one PWM Solar charge controller, and 12V DC power operated lamp solutions, fan, television, radio. Various solar home system packages have been introduced so far, which have offered different product features with price variations. Solar home system size is small, so producing energy is insufficient to fulfill the customer's demand. This research paper presented a novel feature analog PWM solar charging techniques through the algorithm of the fixed frequency current mode controller, which also satisfy the requirements of existing off-grid solar home system users to reduce self-power consumption thus purchasing at an affordable cost. This design set up four periods voltage threshold points as a safeguard for the battery to consider battery voltage level, cable length resistance, battery internal resistance, and EMI (Electromagnetic Interference) effects. PWM solar charging improves the charging strategy by protecting against surge voltage and lightning. The study is divided into three sections: solar charging, regulating signals, and voltage comparator. Accordingly, high-sophisticated fixed-frequency current mode controllers are a noise-free switching gate drive signal with simulation data. The design feature also ignores the EMI (Electromagnetic Interference) noise impact on digital IC's input signals.

Fluorescence tuning, all-optical switching and OR gate realization of phloroglucinol derived carbon dots

Carbon dots that display unusual optical properties are promising materials for photonic applications. Surface passivation of carbon dots improves its optical properties, enabling full-colour emission and excitation dependent emission, making them ideal candidates for bio-imaging. We observed multicolour emission from phloroglucinol-derived carbon dots with surface passivation. Tuning the emission spectra from ultraviolet to visible spectra is achieved with varying surface passivation. Nonlinear optical properties of the samples were studied using spatial self-phase modulation. Power and wavelength dependent variation of nonlinear optical properties are investigated. All-optical switching is achieved from the sample using spatial cross-phase modulation. We have successfully demonstrated an all-optical OR gate with a switch laser and a signal laser. With appropriate control of the switching time, spatial division multiplexing of different signals or different typetypes of data can be encrypted using the same setup. Experimental results show that these carbon dots have better nonlinear optical properties for application in all-optical switching, OR gate and space division multiplexing.

Important Technical Considerations in Design of Battery Chargers of Electric Vehicles

There are many important trade-offs and constraints on cost, volume, weight, conduction losses, switching losses, microcontrollers, isolation, voltage and current levels, voltage and current ripples, battery specifications, charging–discharging algorithms, control system, switch gate drivers, and efficiency of battery chargers in electric vehicles. In this paper, a well-known power electronic topology commonly used in recent relevant studies is considered, and some important technical considerations with regard to the mentioned trade-offs and constraints are discussed in detail for the first time. The discussion concerns the practical and theoretical experiences in implementation of battery chargers and charging stations of electric vehicles exclusively, and it can be extended to various other power electronic topologies.

Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures

We report the fabrication process and performance characterization of a fully integrated ferroelectric gate stack in a WSe2/SnSe2 Tunnel FETs (TFETs). The energy behavior of the gate stack during charging and discharging, together with the energy loss of a switching cycle and gate energy efficiency factor are experimentally extracted over a broad range of temperatures, from cryogenic temperature (77 K) up to 100 °C. The obtained results confirm that the linear polarizability is maintained over all the investigated range of temperature, being inversely proportional to the temperature T of the ferroelectric stack. We show that a lower-hysteresis behavior is a sine-qua-non condition for an improved energy efficiency, suggesting the high interest in a true NC operation regime. A pulsed measurement technique shows the possibility to achieve a hysteresis-free negative capacitance (NC) effect on ferroelectric 2D/2D TFETs. This enables sub-15 mV dec−1 point subthreshold slope, 20 mV dec−1 average swing over two decades of current, ION of the order of 100 nA µm−2 and ION/IOFF > 104 at Vd = 1 V. Moreover, an average swing smaller than 10 mV dec−1 over 1.5 decades of current is also obtained in a NC TFET with a hysteresis of 1 V. An analog current efficiency factor, up to 50 and 100 V−1, is achieved in hysteresis-free NC-TFETs. The reported results highlight that operating a ferroelectric gate stack steep slope switch in the NC may allow combined switching energy efficiency and low energy loss, in the hysteresis-free regime.

Microneedle patch based on molecular motor as a spatio-temporal controllable dosing strategy of L-DOPA for Parkinson’s disease

Controlling medication according to the condition has become a universal treatment regimen for Parkinson's disease (PD) worldwide. However, the general oral administration method is prone to a variety of digestive system discomfort, easy to be broken down by digestive juices and intestinal microorganisms, resulting in low absorption efficiency, and a serious delay in the efficacy of the drug. Here, we developed a microneedle patch (MNP) that could release drugs with controlled temporal and spatial precision triggered by near-infrared (NIR) light for the treatment of PD. The microneedles (MNs) took Gelatin-methacryloy (GelMA) as the matrix, and therapeutic drugs (L-DOPA) were stored in the mesopore of the upconversion micron-rods (UCMRs), dispersing in the GelMA. The molecular motor, as a poreblocker and gate switch, isomerizes under the excitation of ultraviolet and visible light from UCMRs for controlling drug release. This kind of MNP penetrates the epidermis in a painless, non-invasive, and non-infectious way. Under the exposure of NIR light, the L-DOPA in the MNs will be released as needed, and then it seeps into the blood and brain for relieving the symptoms of PD. In the treatment of Parkinson's mice model, this regimen significantly restored motor function, and further mechanistic studies revealed that it reduced neuroinflammation and dopaminergic neuronal death in the substantia nigra. Besides, the released L-DOPA directly entered the blood, which reduces the side effects on the gastrointestinal tract and improves the utilization rate of the drug. These attractive superiorities indicated that the MNP with controlled drug delivery system may be candidate strategies for the treatment of PD and can be used in various related biomedical fields.

Release flux of heavy metals from river sediments at different flow rates

Abstract This paper simulates sediment motion under different hydrodynamic conditions, aiming to investigate the release flux of heavy metals in river sediments. During the lab experiments, carried out in a circular rectangular flume device, water velocity in the flume was altered by controlling the gate switch, and the flow rate was controlled from 0 to 1 m/s. Sediment from the Le'an River and chlorine-removed tap water were used as experimental sediment and water, respectively. Through analyses of Cu, Zn, Cd, and Pb concentration in water at different flow rates, the relationship between the release flux (y) of Cu, Zn, Cd, and Pb and the flow rate (x) was established with a fitting error of less than 15%. In order to judge the reliability of the conclusions, experimental results were verified outdoors. The results showed when the sediment particle size is between 0 and 250 μm, within 1 hour, a quadratic polynomial correlation between the release flux of Cu, Cd, and Pb from river sediments and water velocity when the water pH is 5–9 and the flow rate is 0–65 cm/s; when the water pH is 5–9, the flow rate is 0–35 cm/s, the release flux of Zn from river sediments was shown to have a quadratic polynomial relationship with water velocity. The error between the calculated and measured values of heavy metals released from sediment in the Le'an River were within 5–30%. Our results can provide a theoretical reference for the control and treatment of heavy metal pollution in rivers and further improve corresponding water quality models.

Design and Power Dissipation Consideration of PFAL CMOS V/S Conventional CMOS Based 2:1 Multiplexer and Full Adder

With the integration of circuits, number of gates and transistors are increasing per chip area. However with integration in every digital circuit, the energy due to switching of gate doesn’t decrease at same rate as gates are increased per chip area. Due to this, power dissipation becomes significant and also reduction of heat becomes more complicated and expensive. The CMOS (complementary metal oxide semiconductor) Logic family is preferred for digital circuits due to its performance and impeccable noise margins over other families. However, in CMOS based circuits dynamic power requirement is becoming major concern in digital circuits. The aim ofthis paper is to carry out work that is focused on reducing the power dissipation in circuits, which increases with down scaling of circuits. The experimental work is carried out on 2:1 multiplexer and full adder circuit. Adiabatic logic with positive feedback (PFAL) is applied to redesign the circuit with input power taken as sinusoidal source of 3.3 V and analysis is done for power dissipation between conventional based CMOS circuit and PFAL based CMOS circuit. In comparison with the conventional CMOS based 2:1 multiplexer circuit, the designed PFAL based CMOS 2:1 multiplexer circuit has lesser power dissipation which is measured as 80.871 picoWatts as compared to conventional CMOS circuit which has 6.9090 nanoWatts with the same behavior of circuit. Also for full adder conventional CMOS circuit has 48.0452 picoWatts while PFAL based full adder has 3.9089 picoWatts.

Novel Approach to Measure Internal Power Domain PG Route Weakness

Grid weakness measurement is an extremely important process in the modern-day VLSI design flow. In designs that contain power gating switches, there are additional challenges. It is desirable to find the PG grid weakness of only the gated domain. The tools used in the industry typically measure the total voltage drops from the bump location to the transistor pin. This voltage drop is the summation of the voltage drops in the external domain, switch pin network, and internal domain. This paper explores the ways to measure the internal pin domain voltage exclusively. Ansys Totem tool is used for simulation. Finally, the simulation results are presented to propose the effectiveness and accuracy of the given solution.

Robust Control of Interlinking Converter Using PSO and ABC Algorithms

Objective: In this paper, an optimal control scheme for the Interlinking Converter (IC) system is achieved by the proper regulation of its gate switching functions through appropriate optimal feedback controller design. Methods: Proportional-Integral-Derivative (PID), Fractional Order Proportional-Integral-Derivative (FOPID) and H-infinity loop shaping controller have been designed for the two-fold control objective of simultaneous improvement in system robustness and reduced tracking error using parameter tuning via Particle Swarm Optimization (PSO) and Artificial Bee Colony (ABC) optimization algorithms. Results: The controller parameters are obtained by optimization algorithms. The comparative analysis of the controller performance is carried out through simulation in the MATLAB platform to validate the effectiveness of the controller design under various changing situations. Conclusion: The optimized controller parameters obtained through ABC algorithm are better than that obtained through PSO algorithm in terms of both objective function values and execution time. The resultant robust control strategy for IC system obtained through the H-infinity loop shaping controller provides reduced tracking error and improved stability as compared to PID and FOPID controller, as proved by the simulation results.

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark.

Compute-in-memory (CIM) is an attractive solution to process the extensive workloads of multiply-and-accumulate (MAC) operations in deep neural network (DNN) hardware accelerators. A simulator with options of various mainstream and emerging memory technologies, architectures, and networks can be a great convenience for fast early-stage design space exploration of CIM hardware accelerators. DNN+NeuroSim is an integrated benchmark framework supporting flexible and hierarchical CIM array design options from a device level, to a circuit level and up to an algorithm level. In this study, we validate and calibrate the prediction of NeuroSim against a 40-nm RRAM-based CIM macro post-layout simulations. First, the parameters of a memory device and CMOS transistor are extracted from the foundry’s process design kit (PDK) and employed in the NeuroSim settings; the peripheral modules and operating dataflow are also configured to be the same as the actual chip implementation. Next, the area, critical path, and energy consumption values from the SPICE simulations at the module level are compared with those from NeuroSim. Some adjustment factors are introduced to account for transistor sizing and wiring area in the layout, gate switching activity, post-layout performance drop, etc. We show that the prediction from NeuroSim is precise with chip-level error under 1% after the calibration. Finally, the system-level performance benchmark is conducted with various device technologies and compared with the results before the validation. The general conclusions stay the same after the validation, but the performance degrades slightly due to the post-layout calibration.

Analogous computations in working memory input, output and motor gating: Electrophysiological and computational modeling evidence.

Adaptive cognitive-control involves a hierarchical cortico-striatal gating system that supports selective updating, maintenance, and retrieval of useful cognitive and motor information. Here, we developed a task that independently manipulates selective gating operations into working-memory (input gating), from working-memory (output gating), and of responses (motor gating) and tested the neural dynamics and computational principles that support them. Increases in gating demands, captured by gate switches, were expressed by distinct EEG correlates at each gating level that evolved dynamically in partially overlapping time windows. Further, categorical representations of specific maintained items and of motor responses could be decoded from EEG when the corresponding gate was switching, thereby linking gating operations to prioritization. Finally, gate switching at all levels was related to increases in the motor decision threshold as quantified by the drift diffusion model. Together these results support the notion that cognitive gating operations scaffold on top of mechanisms involved in motor gating.

Numerical simulation of all-optical logic gates based on hybrid-cavity semiconductor lasers.

All-optical switch and multiple logic gates have been demonstrated using a hybrid-cavity semiconductor laser composed of a square microcavity and a Fabry-Perot cavity experimentally. In this paper, two-section tri-mode rate equations with optical injection terms are proposed and applied to study all-optical logic gates of NOT, NOR, and NAND operations utilizing the hybrid-cavity laser. Steady-state and dynamical characteristics of all-optical multiple logic gates are simulated, taking into account the influence of mode frequency detuning, gain suppression coefficients, mode Q factor, injection energy, and biasing current. All-optical logic NOT, NOR, and NAND gates up to 20, 15, and 20 Gbit/s are obtained numerically with dynamic extinction ratios of over 20, 20, and 10 dB, respectively, which are potential response speeds of the all-optical logic gates based on the hybrid-cavity semiconductor lasers.

A 28-GHz Bidirectional Active Gilbert-Cell Mixer in 90-nm CMOS

A bidirectional active mixer based on Gilbert-cell topology is proposed and realized in 90-nm CMOS at 28 GHz. The offered mixer can achieve both the up- and down-conversion under 1-dBm local oscillator (LO) power by adjusting the Gilbert quad switch's gate bias. An IF bidirectional amplifier (IFBDA) is adapted to compensate for the conversion loss (CL) of the Gilbert quad switch. The measured peak conversion gain (CG) is -2.14/-3.28 dB at 28-GHz, and the 3-dB bandwidth is 7/6 GHz in transmit (Tx)/receive (Rx) mode. Total dc power consumption is only 8.4/6.4 mW for Tx/Rx mode under 1.2-V supply voltage. Compared with the traditional bidirectional passive mixers, this mixer demonstrates a low CL with a low LO power.

Relation of Decreased Functional Connectivity Between Left Thalamus and Left Inferior Frontal Gyrus to Emotion Changes Following Acute Sleep Deprivation.

Objective: The thalamus is a key node for sleep-wake pathway gate switching during acute sleep deprivation (ASD), and studies have shown that it plays a certain role in emotion changes. However, there are no studies on the association between the thalamus and emotion changes in ASD. In this study, we used resting-state functional magnetic resonance imaging (R-fMRI) to explore whether changes in the functional connections between the thalamus and other brain regions are related to emotion changes and further explored the function of the thalamus under total ASD conditions.Method: Thirty healthy, right-handed adult men underwent emotional assessment according to the Profile of Mood States Scale and R-fMRI scans before and after ASD. The correlations between changes in functional connectivity between the thalamus and other brain regions and emotion changes were then studied.Results: Positive emotions and psychomotor performance were reduced, and negative emotions were increased following ASD. The functional connections between the left thalamus and left middle temporal gyrus, left inferior frontal gyrus, right thalamus, right inferior temporal gyrus, left middle temporal pole gyrus, right calcarine, left cuneus, left rectus and left medial superior frontal gyrus were significantly altered. Decreased functional connectivity between left thalamus and left inferior frontal gyrus related to emotion changes following ASD.Conclusion: This study finds that functional changes in the thalamus are associated with emotion changes during ASD, suggesting that the left thalamus probably plays an essential role in emotion changes under ASD conditions.