A High-Efficiency Triple-Mode Active Rectifier With Gate Charge Recycling Technique for Wireless Power Transfer System

Abstract

This paper presents an active rectifier design with a gate charge recycling technique. Gate switching increases the switching losses of the active rectifier, therefore, as a way to reduce switching losses, the gate charge recycling technique is proposed. The output power of 15 W is achieved to enable rapid charging using the three standards for wireless charging mode, magnetic induction (WPC and PMA), and magnetic resonance (A4WP). Power-sharing is used to lower the amount of power consumed by each standard mode core. In WPC, and PMA mode zero current sensing (ZCS) technique has been used while in the A4WP mode, the digitally controlled delay adjustment (DCDA) technique has been employed. By using a gate charge recycling block, the efficiency has been considerably improved due to the lower power consumption. It aims to increase the overall efficiency by reusing switching loss using the gate charge recycling block, and it has effectiveness by allowing three standard modes to operate with one single chip. The proposed design combines charge-recycling with zero current sensing techniques to improve power efficiency. The layout size is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.75~\mu \text{m}^{2}$ </tex-math></inline-formula> . The achieved efficiency is 98.6 % in the magnetic induction method (WPC/PMA) at 15 W, and 94.86 % in the magnetic resonance method (A4WP) with an output power level of 15 W. The chip is fabricated in the BCD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS process.