Gate Substrate Research Articles

0.25 μm Trilevel Lithography Using KTI 747 Negative Resist for the Planarizing Layer

In trilevel resist lithography, the thick base‐layer resist serves to planarize the underlying device topography, reduce optical standing wave and E‐beam proximity effects in the imaging resist, and provide an etch mask for pattern transfer into the substrate (1). With shrinking design rules, however, trilevel etched resist features suffer from severe adhesion problems due to the high aspect ratio configuration imposed by dry etching and planarization considerations. Certain negative photoresists such as the polyisoprene KTI 747 is well known for its good adhesion property. This paper describes a trilevel resist process using KTI 747 as the planarizing layer in the trilevel stack for generating 0.25 μm E‐beam exposed CMOS gate features. Results show that KTI 747 can be RIE‐etched with vertical walls. The resist demonstrates good adhesion, low film stress, good step coverage, process compatibility, and adequate etch resistance during the halogenated RIE of the poly‐Si gate substrate. The overall linewidth control after all the lithographic steps for 0.25 μm gates is ∼0.03 μm (3σ) across a 4 in. wafer and ∼0.06 μm (3σ) from wafer to wafer, measured both on the SEM and via electrical probing. This trilevel resist process can also be used with photo‐ or x‐ray lithography.

A temperature-independent capacitance in semiconductor-insulator-semiconductor capacitors

Both measurements of capacitance-voltage (C-V) curves of n− GaAs-undoped AlxGa1− xAs- n+ GaAs (AlGaAs) capacitors at different temperatures, and calculations of C-V curves of semiconductor-insulator-semiconductor (SIS) capacitors at different temperatures, show that there is a temperature-invariant capacitance CC and voltage VC at which C-V curves at different temperatures intersect. We show that this is a general property of SIS capacitors having a degenerate gate and nondegenerate substrate of the same doping type, and that qVC, where q is the electron charge, is approximately equal to the Fermi energy of the degenerate GaAs gate. VC provides a good estimate for the voltage required to establish an accumulation layer on n− GaAs at low temperatures, which is determined from magnetotunneling measurements on AlGaAs capacitors.

On the accuracy of a particular implementation of the Shannon-Buehler method (MOSFET mobility models)

The accuracy of the constant I/sub DS/-V/sub DS/ version of the Shannon-Buehler method is considered. The variation of the effective mobility with gate voltage and substrate bias results in the difference between the measured and actual channel impurity profiles. General expressions that allow one to compute correction factors using different MOSFET mobility models are derived. General results are illustrated by considering two commonly used mobility models.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Gate-edge effects on SPE regrowth from As +-implanted Si

Solid phase epitaxial (SPE) regrowth from selectively As +-implantation-induced amorphous Si is studied. Regrowth dependence on substrate orientations (100) and (111) is clarified using cross-sectional transmission electron microscope (XTEM) analysis. Four gate materials are used: photoresist, poly-Si, silicon dioxide, and silicon nitride. The generation of gate or mask-edge defects strongly depends on the two-dimensional shapes of as-implanted amorphous regions under the gate edge. It depends little on gate materials. When tear-drop shaped or circular amorphous profiles form under the gate edge, defect generation strongly depends on substrate orientations and gate direction. The amorphous regrowth rate in the 〈100〉 direction has an essential role in completely inhibiting such defect formation just under the gate edge.

Series resistance in a MOS capacitor with a thin gate oxide

The effect of series resistance ( R s) on the MOS capacitor high-frequency C– V characteristics has been studied. A new approximate formula for the dependence of bulk series resistance on gate electrode diameter is proposed. The influence of gate dimensions and substrate impurity type on the value of R s is studied. Finally the contribution of back-contact impedance to the total value of the series resistance is discussed.

Determination of the inversion-layer thickness from capacitance measurements of metal-oxide-semiconductor field-effect transistors with ultrathin oxide layers.

The capacitance of ultrathin-oxide (3.4--20.9 nm) large-area square metal-oxide-semiconductor field-effect-transistor devices has been measured at temperatures ranging from 4.2 to 300 K and for a wide range of gate voltages and substrate voltages. The contribution of the inversion layer to the capacitance is as large as 10%. The spatial extent of the lowest-lying inversion-layer subband wave function from the interface, the average inversion-layer thickness, can be determined from these measurements. The results are in semiquantitative agreement with calculations. The carriers are pushed toward the interface with an increase in the carrier density and/or the application of a negative substrate voltage. At elevated temperatures excitation of electrons to higher-lying subbands increases the average inversion-layer thickness and results in a decrease in the measured capacitance.

The effects of constant-current stress on gate oxides in LDD MOSFET's

The constant-current stress between the gate and drain of conventional and LDD MOSFET's is used to study the charging effects of gate oxide in the overlap region and the subsequent degradation of transistor characteristics as a function of spacer width. The voltage needed to maintain a constant current between the gate and the drain is higher for LDD than for conventional structures and increases as the spacer width increases for LDD structures. Added voltage is needed to accumulate the surface under the spacer before electrons can tunnel into the oxide layer. The substrate current versus gate voltage at constant drain bias is studied. In LDD MOSFET's, two maxima are seen; one is reduced by stress, the other (at higher gate voltage) is enhanced.

Transconductance of Silicon-on-insulator (SOI) MOSFET's

Transconductance of n-channel Silicon-on-Insulator (SOI) MOSFET's has been measured with backside gate (substrate) bias as a parameter. For negative values of the backside gate bias, transconductance of SOI transistors is similar to that of bulk devices. On the other hand, transconductance exhibits an unusual behavior when backside gate is positively biased. This is caused by mutual influence between the front-and the backside gate-related depletion zones. Modeling of transconductance using numerical solution of Poisson's equation show good agreement with experimental results.

Channel-length dependence of substrate current characteristic of LDD MOSFET's

The substrate current versus gate voltage characteristic of short-channel LDD structures showed a second peak for large spacer widths and low n-concentrations. The effect of channel length on the two regions of the characteristic (i.e., in the neighborhood of the first and the second peaks) is investigated. While the substrate current at the first peak normalized to the drain current remains independent of the channel length, the normalized substrate current at the second peak increases as the channel length decreases. These observations are explained on the basis of the drain depletion region extended beyond the gate edge. A previously published model by Ko et al. [4] was extended to an LDD structure to quantitatively explain this phenomena.

Dependence of the work-function difference between the polysilicon gate and silicon substrate on the doping level in polysilicon

We correlate the work-function difference φ ps 0between the polysilicon gate and the silicon substrate in an MOS system with the doping level and carrier concentration in polysilicon. Polysilicon was doped by ion implantation with arsenic and phosphorus. The doping level was varied from 1019to 1020cm-3. Hall measurements were used to determine the carrier concentration in polysilicon at a given doping level. The Hall mobility and resistivity as a function of doping level were also obtained. The work function difference φ ps 0was determined by capacitance-voltage measurements on polysilicon-SiO 2 -Si capacitors with different oxide thicknesses. When plotted against the doping level, the work-function difference had a maximum at a dopant concentration of ≈ 5 × 1019cm-3, which corresponds to an electron concentration of 1.5 × 1019cm-3. At higher doping levels the value of φ ps 0decreases. The results can not be fully understood in terms of the Si band structure.

Microwave application of three-terminal Josephson device under hot quasiparticle injection

New effects of quasiparticle injection on microwave irradiated Josephson triodes are demonstrated. The device comprises Pb-insulator (Nb 2 O 5 )-Nb SIS junction with direct contact of the Nb film to n+-GaAs gate substrate. In this device, the very thin Nb film (300 - 600 A) as a base electrode of the SIS detector also serves as an acceptor of the quasiparticles injected from GaAs - Nb Sehottky barrier. The emphasis was placed on injections of hot quasiparticles with the energy in excess of 0.5 eV. The zeroth step height of microwave (10 GHz) irradiated Josephson current I o was efficiently modulated by a sufficiently low density quasiparticle injection current I inj (1 - 2 A/cm2), though no sign of change was found in the superconductive gap parameter and the Josephson critical current itself. These characteristic features became less pronounced as the energy of injected quasiparticles was lowered below 50 meV. Though the present experiment is in a preliminary stage, a current amplification (dI o /dI inj ) of higher than two has been attained on a test specimen.

An impact ionization model for two-dimensional device simulation

A new impact ionization model has been developed for accurate two-dimensional (2D) device simulation to aid VLSI design. The model treats the electron ballistically and so does not assume equilibrium with the local electric field. Furthermore, it includes a degradation of mean free path at the surface, as is commonly accepted for the mobility. The model has been implemented in a 2D device simulator. Calculated substrate current versus gate and drain bias has matched experimental results for channel lengths ranging from 1.5 to 100 µm for both implanted and unimplanted devices of NMOS and CMOS processes. The application of the improved model has led to a greater understanding of the impact ionization phenomenon. First, only a small fraction of the total channel current actually generated the substrate current. This fraction can be as little as 0.1 percent in certain cases, resulting in stringent grid requirements. Second, the broader peak and slower decay of substrate current at high gate bias, seen in the short-channel device, is not due to nearness of the source, as in other short-channel effects (such as threshold voltage shifts, punchthrough), but rather to the increased current density, giving rise to an electric-field component which sustains the impact ionization.

An Impact Ionization Model for Two-Dimensional Device Simulation

A new impact ionization model has been developed for accurate two-dimensional (2D) device simulation to aid VLSI design. The model treats the electron ballistically and so does not assume equilibrium with the local electric field. Furthermore, it includes a degradation of mean free path at the surface, as is commonly accepted for the mobility. The model has been implemented in a 2D device simulator. Calculated substrate current versus gate and drain bias has matched experimental results for channel lengths ranging from 1.5 to 100/spl mu/m for both implanted and unimplanted devices of NMOS and CMOS processes. The application of the improved model has led to a greater understanding of the impact ionization phenomenon. First, only a small fraction of the total channel current actually generated the substrate current. This fraction can be as little as 0.1 percent in certain cases, resulting in stringent grid requirements. Second, the broader peak and slower decay of substrate current at high gate bias, seen in the short-channel device, is not due to nearness of the source, as in other short-channel effects (such as threshold voltage shifts, punchthrough), but rather to the increased current density, giving rise to an electric-field component which sustains the impact ionization.

An analytic and accurate model for the threshold voltage of short channel MOSFETs in VLSI

Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (< 1 μm), substrate bias, and drain voltage. Moreover, comparisons between the developed model and the existing experimental data have been made and good agreement has been obtained. The major advantages of the developed model are that no iterations and no adjustable fitting parameters are required. Therefore, this simple and accurate threshold voltage model will become a useful design tool for ultra short channel MOSFETs in future VLSI implementation.

A Low Noise Preamplifier Using a Tetrode FET in a Novel Feedback Arrangement

This paper describes a low noise n-channel tetrode field effect transistor circuit in which the d.c. input and output voltages of a current integrator are held close to zero. This is achieved by a feedback network to the substrate gate of the tetrode FET. An analysis is made of the circuit arrangement. The application for the circuit configuration is for use in low-noise input stages of nuclear pulse preamplifiers and low frequency preamplifiers used with optical and acoustical detectors. The mutual conductance of the tetrode FET through the input gate is typically 50 mS.

On threshold and flat-band voltages for MOS devices with polysilicon gate and nonuniformly doped substrate

Expressions for the flat-band voltage V FB and threshold voltage V T for MOS devices with polysilicon gate and nonuniformly doped substrate are given. The role of metal-semiconductor contacts and the assumptions involved in the analysis are discussed. Both V FB and V T have three extra terms over the conventional expressions, two terms result from nonuniform doping and one is due to a voltage drop in the gate produced by space charge. Contrasts are made to devices with metal gates and uniformly doped substrates. The commonly used expression for mobile channel charge in terms of gate voltage is clarified.

Substrate Current due to Impact Ionization in MOS-FET

The substrate leakage current vs. gate voltage characteristics of MOS-FET was examined over a wide range of device parameters and measurement conditions. With the increase in the gate voltage, the substrate current increases until it reaches a maximum value. Then it decreases to the value of the generation-recombination current. The substrate current has a high value at low measurement temperatures, high drain voltages, high impurity concentrations of silicon substrates, thin gate-oxide thicknesses and a large drain current. These experimental results were semi-quantitatively explained on the basis of a model in which the substrate current is caused by the first-order impact ionization of the carriers within the pinched-off region. The observed increase of the substrate current is mainly dominated by an increase of the drain current, and the decrease of the substrate current is mainly dominated by a decrease of the impact ionization coefficient.

Subthreshold slope for insulated gate field-effect transistors

An explicit expression has been derived for the subthreshold slope of an insulated gate field-effect transistor. This expression is used to explore the influence of surface band-bending, gate insulator thickness, substrate doping, substrate bias, and temperature.

Thin Film Silicon on Silicon Nitride for Radiation Hardened Dielectrically Isolated Misfet's

The permanent ionizing radiation effects resulting from charge trapping in a silicon nitride isolation dielectric has been determined for a total ionizing dose up to 107 rads (Si). Junction FET's, whose active channel region is directly adjacent to the siliconsilicon nitride interface, were used to measure the effects of the radiation induced charge trapping in the Si3N4 isolation dielectric. The JFET saturation current and channel conductance versus junction gate voltage and substrate voltage were characterized as a function of the total ionizing radiation dose. The experimental results on the Si3N4 are compared to results on similar devices with SiO2 dielectric isolation. The ramifications of using the silicon nitride for fabricating radiation hardened dielectrically isolated MIS devices are discussed.

Dependence of the characteristics of MOS-transistors on the substrate resistivity

The d.c. and small-signal a.c. characteristics of MOS-transistors are studied with particular reference to their dependence on the substrate resistivity. Useful approximate expressions are derived for the drain current and for the gate and substrate transconductances. Expressions are also derived for the self and mutual capacitances associated with the gate and the substrate terminals. Apart from increasing the threshold voltage, an increase in the substrate impurity density is found to reduce the saturation drain current and the gate transconductance but to enhance the substrate transconductance. The total transconductance associated with the gate and substrate and the gate transconductance to drain current ratio are, however, shown to be independent of the substrate resistivity. A heavily doped substrate device is thus shown to be superior to a lightly doped substrate device with regard to the total transconductance to drain current ratio. Results of practical measurements on several n-channel MOS-transistors are presented which support the general validity of the theory and the proposed small-signal equivalent circuit. A simple method is suggested for the determination of the substrate control parameter, A, which is related to the substrate impurity density and gate oxide layer capacitance.