Abstract
The constant-current stress between the gate and drain of conventional and LDD MOSFET's is used to study the charging effects of gate oxide in the overlap region and the subsequent degradation of transistor characteristics as a function of spacer width. The voltage needed to maintain a constant current between the gate and the drain is higher for LDD than for conventional structures and increases as the spacer width increases for LDD structures. Added voltage is needed to accumulate the surface under the spacer before electrons can tunnel into the oxide layer. The substrate current versus gate voltage at constant drain bias is studied. In LDD MOSFET's, two maxima are seen; one is reduced by stress, the other (at higher gate voltage) is enhanced.
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