An Impact Ionization Model for Two-Dimensional Device Simulation

Abstract

A new impact ionization model has been developed for accurate two-dimensional (2D) device simulation to aid VLSI design. The model treats the electron ballistically and so does not assume equilibrium with the local electric field. Furthermore, it includes a degradation of mean free path at the surface, as is commonly accepted for the mobility. The model has been implemented in a 2D device simulator. Calculated substrate current versus gate and drain bias has matched experimental results for channel lengths ranging from 1.5 to 100/spl mu/m for both implanted and unimplanted devices of NMOS and CMOS processes. The application of the improved model has led to a greater understanding of the impact ionization phenomenon. First, only a small fraction of the total channel current actually generated the substrate current. This fraction can be as little as 0.1 percent in certain cases, resulting in stringent grid requirements. Second, the broader peak and slower decay of substrate current at high gate bias, seen in the short-channel device, is not due to nearness of the source, as in other short-channel effects (such as threshold voltage shifts, punchthrough), but rather to the increased current density, giving rise to an electric-field component which sustains the impact ionization.