0.25 μm Trilevel Lithography Using KTI 747 Negative Resist for the Planarizing Layer

Abstract

In trilevel resist lithography, the thick base‐layer resist serves to planarize the underlying device topography, reduce optical standing wave and E‐beam proximity effects in the imaging resist, and provide an etch mask for pattern transfer into the substrate (1). With shrinking design rules, however, trilevel etched resist features suffer from severe adhesion problems due to the high aspect ratio configuration imposed by dry etching and planarization considerations. Certain negative photoresists such as the polyisoprene KTI 747 is well known for its good adhesion property. This paper describes a trilevel resist process using KTI 747 as the planarizing layer in the trilevel stack for generating 0.25 μm E‐beam exposed CMOS gate features. Results show that KTI 747 can be RIE‐etched with vertical walls. The resist demonstrates good adhesion, low film stress, good step coverage, process compatibility, and adequate etch resistance during the halogenated RIE of the poly‐Si gate substrate. The overall linewidth control after all the lithographic steps for 0.25 μm gates is ∼0.03 μm (3σ) across a 4 in. wafer and ∼0.06 μm (3σ) from wafer to wafer, measured both on the SEM and via electrical probing. This trilevel resist process can also be used with photo‐ or x‐ray lithography.