Gate-source Voltage Research Articles

Characterization and modeling of threshold voltage for organic and amorphous thin-film transistors

This work portrays the study and analysis of several extraction techniques that are typically used to ascertain the threshold voltage of organic thin-film transistors (OTFTs) and oxide-based transistors. This study evaluates the effects of physical and electrical parameters such as channel length, doping concentration, temperature, and trap on the threshold voltage (VTH) of both p-type and n-type bottom gate top contact (BGTC) OTFTs using graphical method. The methods employed in the present work to extract the threshold voltage are determined in the linear region of operation and are derived from the drain current (IDS) and the gate-source voltage (VGS) transfer characteristics. To compare and analyze the threshold voltage, various techniques such as the linear extrapolation method (ELR), constant current method (CC), transconductance linear extrapolation method (GMLE), second derivative method (SD), ratio method (RM), Inverse Ratio method (VX), and transition method (TM) are employed in the present work. In addition to DC characterization, the capacitance-voltage (C-V) method was also used to extract and compare the threshold voltage using all the conventional techniques listed above. 2-D numerical simulations were performed to assess the validity and usefulness of the various methodologies used for the extraction of the threshold voltage.

Measurement and gate-voltage dependence of channel and series resistances in lateral depletion-mode β-Ga2O3 MOSFETs

Lateral depletion-mode, beta-phase gallium oxide (β-Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) with source-drain spacings of 3 µm, 8 µm, and 13 µm are studied using a modified transfer length method (TLM) to obtain sheet resistances in the gated and ungated regions as well as to observe their gate electric field dependence. The modified TLM requires the contact resistance to be independent of the gate-source voltage, or changing current density. We verify this by performing measurements on conventional TLM structures in dark and UV conditions and observe a changing current density with constant contact resistance, enabling the development of the proposed method. The conventional and modified TLM give sheet resistances of 20.0 kΩ sq−1 ± 1.0 kΩ sq−1 and 27.5 kΩ sq−1 ± 0.8 kΩ sq−1, respectively. Using a traditional method for determining the channel resistance, the modified TLM improves the convergence of the channel resistances between the three devices, showing higher accuracy than the conventional TLM structures. Gate-source voltage dependence of the sheet resistances is seen in the ungated regions, leading to non-ideal behavior which cannot be observed using the traditional method and conventional TLM structures. These results and analysis methods are important in improving MOSFET parameter extraction and understanding the gate electric field effects on the channel and series resistances in β-Ga2O3 MOSFETs.

Trap characterization of GaN High-electron-mobility Transistors Based on the Transient Drain Voltage

In this work, we presented a comprehensive investigation of the trapping effect in the GaN-based high-electron-mobility transistors (HEMTs) under the negative gate-source voltage condition. The trapping mechanisms in the OFF state were analyzed and the trapping behaviors were characterized using the pulsed measurements preliminarily. Specifically, the transient drain-source voltage curves under a certain filling condition were monitored to reflect the trapping effect in the OFF state. The spectra of time constant and differential amplitude were combined to obtain the information on traps. Three traps with activation energys of 0.467, 0.552, and 0.067 eV were characterized using the transient drain voltage curves under different temperatures. The trap characterization methods may be useful for the further study of the trapping behaviors and can be helpful for the improvement of the reliability of the devices.

An Enhanced Anti-surge Circuit for New Energy Vehicle Electronics System

This paper presents an input surge protection circuit for automotive electronics systems with an adjustable overvoltage protection threshold suitable for high input voltage applications. Compared with the conventional overvoltage protection circuit, it boasts a new high-voltage bandgap reference circuit design without pre-regulation, which takes up less space and can be used on a limited PCB board, expanding the practical application range of the chip. The gate protection circuit can monitor the gate-source voltage of the power MOS in real-time and control the charge pump’s operating mode to improve the system’s safety. The design and simulation of the circuit adopt the 0.18 μm 5V/25V BCD process. The simulation results show that the bandgap reference voltage varies by only 0.38 mV in the input voltage range of 3.5 V-25 V. The quiescent current is 146 uA at 5 V supply voltage. The power MOS can be turned on quickly within 50 us. The overvoltage response time is 599 ns, permitting the circuit to be shut down when a surge occurs.

Effect of Field Plate on Device Performance of Wide Bandgap HEMT

Background: Devices with field plates have gained much popularity in high power and high voltage applications. The work done in this paper is related to designing and studying the different DC and RF characteristics of a field plated GaN HEMT. The results obtained were compared with that of non-field plated GaN HEMT. This comparison and study reported the effect of field plate on device performance. Methods: A GaN HEMT device with and without a field plate was designed and simulated in the SILVACO ATLAS TCAD tool. The performance of both the devices was compared in terms of the exhibited DC and RF characteristics in order to study the effect of the field plate on the device. We have also studied the variation in the cut-off frequency and maximum frequency of both the field plate and without field plate GaN HEMT with respect to gate-source voltage. We have further investigated the device performance by varying the length of the field plate from 0 to 2.5 μm. Results: The study reflects the advantageous feature of GaN HEMT with field plate by exhibiting high breakdown voltage of 292 V in comparison to GaN HEMT without field plate which exhibits a breakdown voltage of 98 V. As a result of using field plate in the GaN HEMT structure, a rise in the Cgs and Cgd capacitances are witnessed. This in turn affects the other RF characteristics of the GaN HEMT with field plate even though the GaN HEMT with and without field plate exhibits nearly same DC characteristics. The field plated GaN HEMT exhibits a reduced cut-off frequency and maximum frequency of 7 GHz and 20 GHz, respectively, in comparison to the GaN HEMT without field plate’s cut-off frequency and maximum frequency of 10 GHz and 25 GHz, respectively. Conclusion: The study reports that using a field plate helps in enhancing the breakdown voltage but at the cost of reduced frequency performance. We have compared our proposed field plated device with different non-field plated devices and concluded that our device exhibits much higher breakdown voltage in spite of reduced device dimension. With the attainment of higher breakdown voltage our proposed GaN HEMT device can be used for high power applications. From the study, it is reported that while increasing the length of the field plate the breakdown voltage also increases. For a particular set of device dimensions, an optimum field plate length provides the highest breakdown voltage but increasing the length of the field plate beyond the optimum value results in reduction in breakdown voltage.

Quasi-Flying Gate Concept Used for Short-Circuit Detection on SiC Power MOSFETs Based on a Dual-Port Gate Driver

The proposed dual-port gate driver architecture relies on a quasi-flying gate concept to protect SiC power MOSFETs against short-circuit events. Hard Switching Faults (HSF) extract charges from the gate by causing a leakage current towards the source, while Faults Under Load (FUL) lead to charge injection into the gate through the reverse transfer capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> ). Such phenomena lead to perturbations of the gate-source voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) which are amplified by the gate resistor, acting as an enhancer of short-circuit signatures. Thus, a small gate resistance is used to ensure high switching dynamics, while a larger one is switched on during PWM on-state operation to identify possible faults. A dual-port gate driver is then proposed to ensure fast switching with HSF and FUL monitoring. The fault detection scheme relies on comparing two thresholds to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> relative changes to the nominal gate voltage. Experimental results using TO-247 package 1.2 kV/36 A SiC MOSFETs exhibit promising inverter leg short-circuit detection and protection against faults in less than 300 ns.

Low concentration hydrogen detection properties of metal-insulator-semiconductor AlGaN/GaN HEMT sensor

In this paper, a Pt/Al2O3/AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) sensor was fabricated for sensing hydrogen (H2) gas and compared to a more conventional Pt-HEMT sensor. The drain-source current (Ids) versus gate-source voltage (Vgs) property (transfer curve) and hydrogen detection characteristics in synthetic air ambient between the HEMT sensor and MIS-HEMT sensor were investigated and compared. It was observed that the MIS-HEMT sensor had a relatively higher resolution in the 100–3000 ppm range than the resolution from 10 to 100 ppm, and a better sensing response for 10 ppm of H2 at 200 ℃ and 225 ℃ using the first-derivative method, which is based on the drain current derivative with respect to time (dIds/dt). When using the real-time method, which is based on the Ids versus time, the measured sensing signal response (recovery) times of the MIS-HEMT with the Al2O3 gate insulator layer reduced to 36 (120) s in comparison to the HEMT sensor values of 44 (175) s. In terms of the dIds/dt method, the response (recovery) time was improved from 4 (2) s to 2 (2) s by using the MIS-HEMT structure.

Potential and electric field analysis of field plated AlGaN/GaN HEMT for high voltage applications using 2-D analytical approach

A physics-based 2-D analytical model is developed for field plated AlGaN/GaN high electron mobility transistor (HEMT) and the effect of field plate on potential and electric field is analyzed. The complete generalized theory developed includes the dependence of electric field and electric potential distribution on (i) different dielectric materials and (ii) dielectric thickness below the field plate. An extensive study of the effect of various non-field plate parameters such as doping concentration in the AlGaN layer, drain source voltage, and gate source voltage has also been carried out. It is observed that with the introduction of field plate, primary peak of electric field gets reduced and redistribution of electric field occurs in a better way with the introduction of much smaller secondary electric field peak. This leads to improved breakdown voltage thus making the device suitable for high voltage applications. The analytical results are also compared with the simulated results extracted with ATLAS 2D device simulation. The good agreement validates the analytical approach.

Capacitance Variations and Gate Voltage Hysteresis Effects on the Turn-ON Switching Transients Modeling of High-Voltage SiC MOSFETs

This paper presents a discrete and real-time capable dynamic behavioural model of the turn-on switching transition of high-voltage and high-current Silicon Carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) half-bridge power modules. The dynamic switching model utilizes the Shichman and Hodges equations using voltage-dependent non-linear device capacitances and module electrical parameters to obtain an accurate dynamic model of the device switching transients. The key device states gate-source voltage, drain current and drain-source voltage are modelled. The paper investigates the impact of correct device capacitance modelling with low off-state gate-source voltage values, impacting the device capacitances and causes gate-voltage hysteresis effects. It has been shown that the presented discrete-time dynamic switching model accurately describes the turn-on transient and the results highlight the importance of correct capacitance and threshold voltage characterization data. The modelling results are compared to experimental measurements conducted in a 3.3 kV/750 A SiC MOSFET power module. The model exhibits an average accuracy of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim 4\%$</tex-math></inline-formula> for turn-on energy and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim 1.3\%$</tex-math></inline-formula> for the turn-on time compared to measurements. These models are valuable for rapid and cost effective design and validation of advanced gate-driver circuits and for determining key design and operating parameters such as deadtime, switching frequency and switching losses.

Review of Short-circuit Protection Circuits for SiC MOSFETs

Silicon carbide (SiC) metal-oxide-semiconductor field effect transistors (MOSFETs) are commonly used in the power transistor industry owing to their superior conductivity, low switching loss, high-frequency operation, and desirable thermal characteristics. However, the short-circuit withstand time of SiC MOSFETs is shorter than that of Si devices, which is disadvantageous in fault states. Gate drivers for SiC MOSFETs require short-circuit protection and soft termination circuits to detect short circuits and protect the power devices and systems from a short-circuit state. Thus, short-circuit protection circuits for SiC MOSFETs are reviewed in this paper. Accordingly, short-circuit detection circuits classified according to gate-source voltage (VGS), drain-source voltage (VDS), and drain-source current (IDS) detection methods are discussed. Moreover, the merits and demerits of soft termination circuits are reviewed.

Evaluation of the Thermal Resistance in GaN HEMTs Using Thermo-Sensitive Electrical Parameters

The thermal management of power converters is not only crucial for their own optimal operation and reliability, but also for the overall system in which they are operating. Reliability is a very serious aspect because power electronics systems are being increasingly widely adopted in mission-critical applications in the e-mobility sector, in smart grids, and other applications where safety and operational continuity are essential. The current trend towards miniaturization of power conversion systems and, consequently, towards high power density solutions is speeding up the diffusion of Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT). GaN HEMT-based high power density converters must be properly managed, making the estimation of the thermal characteristics of these devices essential. This paper proposes the use of some Thermo-Sensitive Electrical Parameters (TSEP) for a simple and effective thermal resistance evaluation. The primary advantages and limitations of these TSEPs have been critically analyzed. The analysis highlighted that the use of the gate-source voltage is the best approach. However, it requires direct access to the gate pin, which may not be available externally in some system-in-package solutions.

Investigation on safe-operating-area degradation and failure modes of SiC MOSFETs under repetitive short-circuit conditions

• Repetitive short circuits cause thermal runaway failure of SiC MOSFETs • Safe operating area reduces after repetitive short-circuit conditions • Repetition frequency and duration affect degradation of SiC MOSFETs • Hole traps in gate oxides induce degradation of SiC MOSFETs The safe operating area is an operating area with high reliability for SiC MOSFET, and its degradation may cause power electronic system failure. The safe-operating-area degradation and the failure modes of 1200V/66A SiC MOSFET caused by repetitive short-circuit stress with different short-circuit times and short-circuit time intervals are investigated. A short circuit test platform with circuit protection is configured to degrade DUT(device under test), and the safe operating area is characterized after repetitive short circuit stress is applied. The degradation mechanism of the safe operating area is explained by the 1-D electro-thermal coupling model based on Sentaurus TCAD. When the critical short-circuit duration is 12μs, the single short-circuit failure mode of DUT with 400V dc-bus voltage is a gate-source short-circuit failure. From the short circuit test result, the failure modes under repetitive short-circuit conditions include gate-source short-circuit failure and thermal runaway, depending on the repetitive short-circuit time intervals. For the same short-circuit time interval, when the short-circuit duration is 10μs, the weakest boundary of the safe operating area is the blocking voltage. When the short-circuit duration is 2μs, all three boundaries of the safe operating area are contracted. These results are confined to 400V dc-bus voltage, 25°C case temperature, and 18V/-3V gate-source voltage. Schematic diagram of the degradation of the safe operating area of the device under long-term operating conditions. (a) Small margin, failure (b) Large margin, high cost (c) Optimal design

Accurate SiC MOSFET Chip Extraction Based on Parasitic Parameter Impact Compensation

With the growing use of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> in power electronic equipment, it is meaningful to extract precise typical waveforms and characteristics for device manufacture, converter design, and operating evaluation. Many solutions have been proposed to improve measurement precision by equipment and essential techniques. However, the measured object should also be accurately identified as the existing measurement result consisting of the expected gate-source voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) and voltage drops on parasitic parameters between measuring points. This article, first, reveals the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> measurement deviation of TO-247-4 and TO-247-3 devices during the switching process and crosstalk, based on the equivalent circuit model and simulation waveforms. According to the clarification of the measured object, an improved <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> extraction method is proposed to eliminate this deviation. Voltage drops on parasitic parameters are compensated, with the help of high-precision equipment and the proven parasitic parameter extraction technique. Experiments are constructed to verify the analysis of measurement deviation and the availability of the proposed method. Comparison between various operating conditions emphasizes its necessity, especially in high-capacity and low-driving-resistor applications, contributing to characterization, operating condition monitoring, protection design, and measurement understanding of wide band-gap devices.

Real-Time FPGA Simulation of High-Voltage Silicon Carbide MOSFETs

This article presents a real-time field-programmable gate array (FPGA)-based dynamic model of high-voltage and high-current silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor ( <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> ) half-bridge power modules. The dynamic switching model utilizes the Shichman and Hodges equations using voltage-dependent nonlinear device capacitances and module electrical parameters to obtain an accurate dynamic model of the device switching transients. The key device states gate-source voltage, drain current, and drain-source voltage are modeled and discretized using forward Euler discrete integration method. Analysis of synthesizing the discrete-time model into real-time FPGA-based system with real-time data output from the on-board digital-to-analog converter is presented in detail. The model is utilized in modeling a 320-kW, medium-voltage dc/dc dual-active bridge converter and verified using dynamic experimental results from a 3.3-kV SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> half-bridge power module. It has been shown that the presented discrete-time dynamic switching model accurately describes the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> and turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> switching transients of the SiC power module at various voltage and current levels. Such models are useful for rapid and cost effective design and prototyping of SiC-based power electronic systems by defining key design and operating parameters, such as deadtime, switching frequency, and switching losses.

Parameters Design and Optimization of SiC MOSFET Driving Circuit with Consideration of Comprehensive Loss and Voltage Stress

In conventional parameters design, the driving circuit is usually simplified as an RLC second-order circuit, and the switching characteristics are optimized by selecting parameters, but the influence of switching characteristics on the driving circuit is not considered. In this paper, the insight mechanism for the gate-source voltage changed by overshoot and ringing caused by the high switching speed of SiC MOSFET is highlighted, and we propose an optimized design method to obtain optimal parameters of the SiC MOSFET driving circuit with consideration of parasitic parameters. Based on the double-pulse circuit, we evaluated the influence of main parameters on the gate-source voltage, including driving voltage, driving resistance, gate parasitic inductance, and stray inductance of the power circuit. A SiC-based boost PFC is constructed and tested. The test results show that the switching loss can be reduced by 7.282 W by using the proposed parameter optimization method, and the over-voltage stress of SiC MOSFET is avoided.

All-Carbon Solution-Gated Transistor with Low Operating Voltages for Highly Selective and Stable Dopamine Sensing.

The diversity of carbon materials makes it possible to prepare all-carbon electronic devices requiring components with different properties and functions. In this work, we fabricate an all-carbon solution-gated transistor (AC-SGT) based dopamine (DA) sensor with Nafion coated nitrogen and oxygen co-doped carbon yarn (Nafion/NOCY) as the gate electrode and graphene as the channel. The carbon materials in AC-SGT render the usage of a variety of strategies to improve its electrochemical sensing capability including the modification of the gate electrode and the modulation of the operating voltage. With a low gate-source voltage of 0.02 V as well as a low drain-source voltage of 0.05 V, AC-SGT manifests the outstanding DA sensing performances in terms of sensitivity, selectivity, limit of detection (3 nM, S/N > 3), linear range (3 nM to 300 μM), long-term stability (over 30 days), and preconditioning time (60 s). Furthermore, a smartphone controlled portable sensing system integrated with AC-SGT is fabricated herein, which shows the excellent in vitro sensing capability of DA in urine, proving the potential of all-carbon transistors in smart wearable biosensors.

Analysis of Dead-Time Energy Loss in GaN-Based TCM Converters With an Improved GaN HEMT Model

For gallium nitride (GaN) based triangular current mode (TCM) applications, the dead-time has a significant effect on the switching loss. However, previous GaN high electron mobility transistor (HEMT) models focus on the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on/off</small> process without fully considering the effect of the dead-time. Hence, this article analyzes the switching transients under the superfluous and insufficient dead-time and evaluates the dead-time loss with an improved GaN HEMT model. The proposed model improves an existing GaN HEMT model by adding the voltage rising/falling time of the gate driver, the dynamic threshold voltage of Schottky-type GaN HEMTs, and an equivalent gate-drain capacitance obtained from the datasheet. Verified by a GaN-based double-pulse test, the proposed model can more accurately calculate the gate-source voltage and the self-commutated reverse conduction voltage. Verified by a GaN-based TCM Buck converter, the proposed model can predict the dead-time loss well and has higher simulation accuracy for the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> process induced by the inappropriate dead-time.

A Suppression Method for Gate-Source Voltage Oscillation With Clamping Function for GaN Devices

Gallium nitride (GaN) devices are generally more prone to severe switching oscillations than Si <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfets</small> due to their fast switching speeds. Different from Si and SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfets</small> , GaN devices typically have a lower maximum gate voltage rating. Taking the Efficient Power Conversion Corporation series as an example, the gate drive voltage is usually 5 V, but the maximum voltage rating is 6 V. Therefore, GaN devices are more susceptible to damage from gate-source voltage oscillation. In this letter, a gate drive circuit with a clamping function is proposed to suppress gate-source voltage oscillation. The adopted method can not only clamp the gate voltage of the GaN device near the drive voltage to protect the device, but also does not affect the switching speed of the device. The proposed method mainly uses some passive components that make the circuit design simpler compared with other active gate driver methods. Finally, the effectiveness of the proposed method is verified by experiments.

Gate Drive Circuit Suitable for a GaN Gate Injection Transistor

A GaN gate injection transistor (GIT) has great potential as a power semiconductor device. However, a GaN GIT has a diode characteristic at the gate-source, and a corresponding gate drive circuit is thus required. Several studies in the literature have proposed the gate drive circuits with the speed-up capacitors, but adding these capacitors complicates the gate drive circuit, and increases both the drive and reverse conduction losses. Moreover, driving a GaN GIT with such gate drive circuits becomes more susceptible to the false turn-on. In this paper, a gate drive circuit suitable for a GaN GIT without a speed-up capacitor is proposed. This type can provide the high-speed switching, and exhibit the low gate drive loss and reverse conduction loss. The proposed circuit also has high immunity against the false turn-on and stable gate-source voltage before and after startup. The drive loss of the proposed type is calculated and its validity is confirmed experimentally. Furthermore, the drive loss of the proposed type is compared with the conventional circuits. The result shows that the drive loss of the proposed type is improved by up to 50 %, compared with the conventional type. Finally, the proposed type is experimentally tested to drive a buck converter at the switching frequency of 150 kHz. The entire loss of the converter can be reduced by up to 9.2% at 250 W, compared with the conventional type.

Large Size Few-Layer Ambipolar MoS&lt;sub&gt;2&lt;/sub&gt; Metal-Oxide-Semiconductor Field Effect Transistors by Nitrogen Plasma Doping

Molybdenum disulfide (MoS2), a typical two-dimensional layered semiconductor material, is widely studied due its excellent electronic properties in atomic scale. In this study, we achieved the growth of large size few-layer MoS2 films by using molybdenum boat with vertical shield at the end to carry MoO3 precursor in the chemical vapor deposition (CVD) system. The optical microscopy reveals the morphology and lateral size of as-grown films. The Raman spectrum testified that the synthesized films are few-layer MoS2 with defects. Metal-oxide-semiconductor field effect transistors (MOSFETs) based on CVD-grown MoS2 are fabricated, presenting n-type transportation with ION/IOFF ratio about 103. The transportation behaviour of MoS2 MOSFETs is changed from n-type to ambipolar by introducing nitrogen plasma into MoS2 films. The electron or hole transportation in MoS2 is controlled by gate-source voltage. The ambipolar MOSFETs show ION/IOFF ratio about 103.