Abstract

The proposed dual-port gate driver architecture relies on a quasi-flying gate concept to protect SiC power MOSFETs against short-circuit events. Hard Switching Faults (HSF) extract charges from the gate by causing a leakage current towards the source, while Faults Under Load (FUL) lead to charge injection into the gate through the reverse transfer capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> ). Such phenomena lead to perturbations of the gate-source voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) which are amplified by the gate resistor, acting as an enhancer of short-circuit signatures. Thus, a small gate resistance is used to ensure high switching dynamics, while a larger one is switched on during PWM on-state operation to identify possible faults. A dual-port gate driver is then proposed to ensure fast switching with HSF and FUL monitoring. The fault detection scheme relies on comparing two thresholds to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> relative changes to the nominal gate voltage. Experimental results using TO-247 package 1.2 kV/36 A SiC MOSFETs exhibit promising inverter leg short-circuit detection and protection against faults in less than 300 ns.

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