Gate Overlap Research Articles

Design and Investigation of Gate Overlap Step Shape Double Gate (SSDG) TFET for Photosensing Applications

Design and Investigation of Gate Overlap Step Shape Double Gate (SSDG) TFET for Photosensing Applications

Analysis on performances of ultra-thin vertical MOSFET depending on position of gate–drain misalignment

In advanced MOSFET design, a vertical-channel structure provides the advantages of a smaller footprint of the transistor cell and stronger immunity against short-channel effects by introducing higher freedom in determining the channel length. For these reasons, vertical devices are still predicted to be an upcoming solution in the most recent technology roadmap. However, due to the cell-to-cell or wafer-to-wafer processing deviation that inevitably exists, it can be quite challenging to locate the gate edges at the exact positions that maximize the device performance. In this work, a series of technology computer-aided design (TCAD) device simulations have been carried out to investigate the effects of gate underlap and overlap structures on the device performance of vertical-channel MOSFETs. The device characterizations were conducted from the aspects of both DC and HF operations for higher completeness of this work, since both are not usually optimized at the same time under the same structural and processing conditions. Under the underlap condition, slight degradation in the on-state current (I on) drivability was observed. On the other hand, a noticeable off-state current (I off) increase was witnessed under the underlap conduction. It is explicitly demonstrated that excessive gate underlap results in non-ideal effects, including degradation of the subthreshold swing (S), worsening of drain-induced barrier lowering, and lowering of the maximum transconductance (g m,Max). In the HF analyses, although f T and f max remained high under overlap and gate–drain alignment conditions, it was observed that both were likely to deteriorate under underlap conditions. As a result, a processing margin in the anisotropic etching of the gate can be obtained for the optimization of the DC and HF performance of vertical-channel MOSFETs, paving the way for a wide variety of low-power and high-speed analog and digital applications.

Analysis of thermal stability in underlap and overlap DMG FinFETs including self-heating effects

This work investigates the impact of the self-heating effect (SHE) on SOI Dual-Material Gate (DMG) FinFETs with channel engineering including gate underlapped and overlapped structures. Both these structures are compared with conventional DMG FinFET to detect the possible effects of SHE on DC characteristics and thermal parameters. The drop rates of ON current (ION), Off-current (IOFF), Maximum transconductance (gm,max), ION/IOFF ratio, and Drain-induced barrier lowering (DIBL) are calculated to get the precise results. For extensive thermal reliability analysis, the two main distinguishing parameters lattice temperature and thermal resistance are also calculated and their dependency with gate/drain bias and operating temperature are also explored. Comparison between thin and thick BOX devices aimed at distinguishing possible effects of SHE on BOX thickness variation. The result shows that the SHE greatly improves ION/IOFF ratio by 220.8% in gate underlap structure due to large reduction in leakage current. Although lattice temperature is higher in gate overlap structure but thermal resistance decreases by 53.6 % due to its high ON current. Using high-k dielectric BOX materials, small improvement in device SHE characteristics is also accomplished.

Design and Performance Analysis of Gate Overlap Dual Material Tunnel Field Effect Transistor

Design and Performance Analysis of Gate Overlap Dual Material Tunnel Field Effect Transistor

Analysis on the impact of interface Trap distributions on SOI DMG FinFETs: Overlap/underlap configurations

This paper investigates the significance of interface trap charges (ITCs) distribution by introducing localized charges (donor/acceptor) at the interface of semiconductor/insulator on dual-material gate (DMG) FinFETs in gate Overlap and Underlap configurations in terms of DC and analog/RF parameters. Different charge density profiles like Uniform and Gaussian distribution of traps are considered at different energy levels for both donor and acceptor ITCs to evaluate the devices reliability. It is observed that the donor traps mainly affects the OFF-state current (IOFF) by insignificantly, while, acceptor traps mainly impacts ON state current significantly. The impact of Acceptor ITCs on various parameters such as transfer characteristics, electron density, conduction band energy, transconductance (gm), total gate capacitance (Cgg), device efficiency (gm/ID), and cut-off frequency (fT), for DMG FinFETs have been comprehensively analysed at trap concentration N0=1×1013 and compared with no traps among the three devices. An acceptor trap charges with Gaussian distribution has larger impact on devices performance. It degrades the ON state-current by 36.09 %, 25.72 %, and 41.9 % for conventional, Overlap, and Underlap configurations, respectively. It is evident from the results DMG underlap configuration is more vulnerable to ITCs, attributed to its larger interface charge region due to the increase in effective channel length while, the overlap configuration is more immune towards ITCs as, lesser electrons get trapped. Thus, the overlap configuration is the most reliable among underlap and conventional configurations.

Quality factor and digital inverter performance in gate underlap and overlap DMG FinFETs

This paper presents a comparative 3D simulation study of Quality factor among Gate Underlap and Overlap techniques in both Si and Ge Dual Material Gate (DMG) FinFETs using the Sentaurus TCAD tool. The results of both the techniques are carefully examined and compared with Conventional DMG FinFET to analyze the performances of these devices. The effect of gate overlap/underlap techniques on threshold voltage (Vth), ION/IOFF ratio, drain induced barrier lowering (DIBL), transconductance (gm), subthreshold swing (SS), and Quality factor (Q) are investigated. It is found that Ge DMG FinFETs have higher gm and quality factor values as compared to Si DMG FinFETs. The prospects of these techniques in low-power digital applications have been performed by implementing complementary Si DMG FinFET based inverter circuit. We have extracted the average delay and noise margin, where the overlap structure performs better such as high current gain and no overshoot/undershoot peaks in the transient characteristics.

Effect of ITC on Boolean functionality of n-type heterojunction vertical TFETs

The objective of this paper is to investigate the effect of interface trap charges (ITC) on Boolean functionality of n-type vertical TFET structure with and without gate overlap (HJ-VTFET-WG and HJ-VTFET-WOG). For this, the logic gates are designed using HJ-VTFET by considering germanium as source material. Our simulations results have shown that two input logic functions such as AND and OR gates can be successfully implemented using HJ-VTFET-WG and HJ-VTFET-WOG structures. The two key concepts are utilized for achieving logic functionality of proposed vertical TFET such as change in gate–source overlap area and appropriate selection of silicon body thickness. Thereafter, the AND and OR functionality are examined using drain current characteristic and energy band diagram of HJ-VTFETs under different trapped charges. With positive ITC, the logic functions have a smaller tunneling width and a larger tunneling width with negative ITC. It is found that positive ITCs can improve device features, whereas, negative ITCs degrade device performance. Further, the electrical performance of HJ-VTFET-WG is less susceptible to interface trap charges than HJ-VTFET-WOG which indicates that the proposed HJ-VTFET-WOG structure is a potential candidate for designing the logic gates for digital application under ITC effect.

Enhancing subthreshold slope and ON-current in a simple iTFET with overlapping gate on source-contact, drain Schottky contact, and intrinsic SiGe-pocket

In this paper, we present a new novel simple iTFET with overlapping gate on source-contact (SGO), Drain Schottky Contact, and intrinsic SiGe pocket (Pocket-SGO iTFET). The aim is to achieve steep subthreshold swing (S.S) and high ION current. By optimizing the gate and source-contact overlap, the tunneling efficiency is significantly enhanced, while the ambipolar effect is suppressed. Additionally, using a Schottky contact at the drain/source, instead of ion implantation drain/source, reduces leakage current and thermal budget. Moreover, the tunneling region is replaced by an intrinsic SiGe pocket posing a narrower bandgap, which increases the probability of band-to-band tunneling and enhances the ION current. Our simulations are based on the feasibility of the actual process, thorough Sentaurus TCAD simulations demonstrate that the Pocket-SGO iTFET exhibits an average and minimum subthreshold swing of S.Savg = 16.2 mV/Dec and S.Smin = 4.62 mV/Dec, respectively. At VD = 0.2 V, the ION current is 1.81 times 10–6 A/μm, and the ION/IOFF ratio is 1.34 times 109. The Pocket-SGO iTFET design shows great potential for ultra-low-power devices that are required for the Internet of Things (IoT) and AI applications.

Electrical Characterization of Multi-Gate MOSFET with Reduced Short-Channel Effects for High-Power Applications

The double-gate MOSFET is proposed for high-voltage and high-power applications with decreased short-channel effects (SCEs) and drain current with gate overlap. This model explicitly incorporates the SCEs for thin-layered MOSFETs with large drain regions. The device’s short-channel effects are decreased through the drain-resistance effect present in the device. The gate contact overlapped region significantly affects the device operation for high-voltage FETs. These effects are modeled by self-consistent solutions of available multigate MOSFET device models with potential distribution. The demonstrated model can be further applied for size limitations in the modeling of multigate MOSFETs.

Ambipolarity Suppression of Band Gap and Gate Dielectric Engineered Novel Si0.2Ge0.8/GaAs JLTFET Using Gate Overlap Technique

Ambipolarity Suppression of Band Gap and Gate Dielectric Engineered Novel Si0.2Ge0.8/GaAs JLTFET Using Gate Overlap Technique

Investigation on Effect of Interface Trap Charges and Temperature in Gate Overlap Graphene Source Step Shape Double Gate Tunnel FET

Abstract This work evaluates the electrical parameters of Gate Overlap Graphene source Step Shape Double Gate TFET (GO-GR-SSDG-TFET) with wide variation in interface trap charges (ITCs) and temperature. Here, both the positive interface charges (PITCs) and negative interface charges (NITCs) along with temperature ranges from 200-500 K on DC, RF/analog and linearity characteristics are analyzed using TCAD Sentaurus Simulator. It is observed that there is improvement (degradation) in current ratio, transconductance, gain, cut-off frequency, and delay with increase (decrease) in PITC (NITC), whereas, opposite trend is realized in terms of linearity parameters. The rise in temperature leads to degradation is subthreshold behaviour due to exponential characteristic of Shockley-Read-Hall (SRH) recombination with temperature. It is also seen that at high temperature there is degradation transconductance, device efficiency, cut-off frequency, current ratio, delay, and temperature sensitivity (ST) in the proposed TFET. Moreover, the linearity parameters are degraded with rise in temperature. Finally, a comparison table is highlighted in terms of various electrical parameters for proposed TFET with existing data.

Influence of Semiconductor Island Geometry on the AC Performance of Flexible InGaZnO TFTs

The AC performance of flexible TFTs sufferers from parasitics caused by tolerances needed for the fabrication on free-standing plastic foils. In this context, the semiconductor island can either be wider or narrower than the source/drain contacts. Traditionally, the second configuration is expected to result in faster TFTs as the total gate overlap area is smaller. However, here it is shown that 2.5 μm long flexible InGaZnO TFTs with wide semiconductor islands exhibit better frequency performance such as a f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 26.1MHz (compared to f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 13.8MHz of TFTs with narrow semiconductor islands). This effect is confirmed for flat and bend TFTs and is caused by current spreading in the semiconductor islands, as well as the frequency dependency of the gate capacitance.

Performance Investigation of GaSb/Si Heterojunction based Gate Underlap and Overlap Vertical TFET Biosensor.

The present paper estimates the performance of vertically developed double gate GaSb/Si tunnel field-effect transistor (V-DGTFET) biosensor with source pocket. A commercially accessible tool, Silvaco-TCAD, is exploited for carrying simulations of V-DGTFET. The device's novelty is deploying a material with a small bandgap, namely GaSb, in the source region to improve the carrier tunneling in source-channel (GaSb-Si) heterojunction. Further, the present work has analysed the performance on half gate underlap and half gate overlap V-DGTFET based label-free biosensor. The performance of V-DGTFET biosensor corresponding to various biomolecules such as APTES with κ=3.57, bacteriophage-T7 with κ=6.4, apomyoglobin with κ =8.1 and gelatin with κ=12 is investigated with reference to energy band diagram, potential profile, electric field and drain characteristics. Furthermore, by considering the different values of dielectric constants from 1 to 12, the present paper computed the figure of merits (FOMs) essentially linearity and sensitivity. The results demonstrated that neutral biomolecules with higher dielectric constant values showed higher sensitivity compared with other biomolecules. Moreover, it is estimated that gelatin has to drain current sensitivity of 5.6×105, which is 13%, 20%, and 41% more in comparison to apomyoglobin (κ =8.1), bacteriophage-T7 (κ=6.4), and APTES (κ =3.57) sensitivity at 15 nm cavity length.

Modeling, simulation investigation of heterojunction (GaSb/Si) vertical TFET-based dielectric modulated biosensor structure

In this article, an analytical model for dielectric modulated heterojunction (GaSb/Si) vertical tunnel field-feect transistor (DMH-VTFET) based biosensor has been developed and investigated for its biological applications. The presented analytical model incorporates important parameters of biological molecules i.e. dielectric permittivity which provides a generalized view of the physical electrostatics and electrical characteristics of the DMH-VTFET biosensor. Biomolecule immobilization within the cavity causes a change in electrical attributes like surface potential and drain current. It has been analyzed that the various factors (including variations in applied voltages (Vds and Vgs)) results in an impact on the device's electrical characteristics. The results have been validated by comparing the characteristics of the modeling output with simulated outcomes. Furthermore, in this work, the functionality of a label-free biosensor based on a gate overlap DMH-VTFET has also been investigated. The functionality of the DMH-VTFET biosensor is examined with reference to the potential profile, energy band diagram, and drain characteristics for various biomolecules, including Zenin (KC = 7), APTES (KC = 3.57), Gelatin (KC = 12), and Keratin (KC = 10). The substrate layer is divided into eight segments, including source- and drain-depleted segments, to produce the potential model. The pseudo-1-dimensional and 2-dimensional versions of Poisson's equation (PE) are used, respectively, to resolve the potential of each segment. The PEs at the intersegment of various segments are solved using the parabolic approximation process. The Silvaco ATLAS tool is used to recreate the biomolecules using various dielectric constant values for simulation results at technology computer-aided design (TCAD).

Impact of self-heating on RF/analog and linearity parameters of DMG FinFETs in underlap and overlap configurations

In this paper, the influence of self-heating effect (SHE) on the performance of Silicon on Insulator (SOI) dual material gate (DMG) FinFETs in underlap and overlap configurations for RF/analog applications is reported using three-dimensional TCAD simulators. The increase in electron velocity at channel surface is due to reduce effective electrical field at drain end, resulting in smaller DIBL and hot carrier effects. The device insights are reported by electron velocity, lattice temperature, thermal resistance, and output conductance versus frequency profiles. The findings on analog/RF figures of merit such as transconductance (gm), output conductance (gd), intrinsic gain (Ai), gate capacitance (Cgg), intrinsic delay (τ), cut-off frequency (fT), transconductance generation factor (TGF), gain frequency product (GFP), transconductance frequency product (TFP), and gain transconductance frequency product (GTFP) are reported with and without SHE. The results show that analog performance of Conventional and Underlap structures are improved but the influence of SHE is more deteriorating on Overlap structure. Furthermore, the linearity performance parameters VIP2, VIP3, IIP3, and 1 dB compression point are degraded with self-heating is due to increase in gm2 and gm3 values. It is seen that the gate overlap structure exhibits higher ON state performance which even after deterioration with Self-heating is still better than its counterparts as it has better gate controllability stemming from its lower effective channel length.

Analysis on electrical parameters including temperature and interface trap charges in gate overlap Ge source step shape double gate TFET

In this paper, the electrical parameters are evaluated for the variations of temperature in Gate Overlap Ge source Step Shape Double Gate TFET (GO-Ge-SSDG-TFET) under the impact of interface trap charges (ITCs). Here, the effect of positive ITC (PITC) and negative ITC (NITC) with wide variation in trap concentrations along with variation in temperature (200–500 K) on DC, RF/analog, and linearity behavior are studied using TCAD simulator. It is found that there is up-gradation (degradation) in current ratio (ION/IOFF, ION/IAMBP), cut-off frequency (ft), and linearity parameters with PITC (NITC). At low gate voltage, there is degradation in OFF-state behavior with increased temperature and this is due to exponential dependence of temperature with Shockley-Read-Hall (SRH) recombination. Moreover, at high gate bias, Band to Band tunneling (BTBT) is dominant, which is weak temperature dependence and leads to negligible variation in drain current. The OFF state current is degraded by the order of 109 as temperature is increased from 200 to 500 K. At high temperature, the up-gradation in ft and intrinsic delay (τ) indicates improvement in device characteristic.

A low gate charge field-plate trench MOSFET with hollow split gate structure

We propose a high-performance field-plate trench MOSFET featuring hollow split gate structure in this paper. By reducing the overlap of control gate to split gate without additional masks and preserving the stepped split gate structure, it is confirmed that the parasitic gate capacitance and gate charge are significantly reduced without changing the control gate structure and influencing the electric field distribution of drift region. Compared with the conventional two-step-oxide field-plate trench MOSFET, TCAD numerical simulation results show that gate-source charge (Qgs) and gate charge (Qg) (Vgs = 10 V) of the proposed device with a breakdown voltage of 94.32 V are reduced by 20.94% and 13.59%, respectively. Besides, breakdown voltage (VB) and specific on-resistance (Ron,sp) of the proposed device remain almost constant because of the retained sidewall of hollow split gate. In addition, it is observed that the average total power loss of the proposed device is reduced by 4.60%–8.06% when frequency ranges from 100 kHz to 1 MHz in comparison to that of the conventional one.

Impact of gate overlap and underlap on analog/RF and linearity performance of dual-material gate-oxide-stack double-gate TFET

Impact of gate overlap and underlap on analog/RF and linearity performance of dual-material gate-oxide-stack double-gate TFET

Investigation of gate-source overlap impact on the performance of different SOI-TFETs with T-shaped channel

This paper presents three different structures of SOI-TFET. Using silicon and germanium as source material and placing a high-doped [Formula: see text] layer at the source/ channel interface, these different structures are formed. All of the architectures have a [Formula: see text]-shaped channel and the thickness of the source and drain regions are less than the channel thickness. At first, the impact of gate-to-source overlap on the DC performance metrics of these tunneling field-effect transistor (TFETs) is investigated by 2D numerical simulations. The results indicate that the gate overlap on the source can improve the performance of the devices with [Formula: see text]-shaped channels. Then, the proposed structures have been analyzed in terms of AC analysis when the overlap of the gate on the source is 50%. It is confirmed that the Ge-source [Formula: see text]-channel SOI-TFET with gate-source overlap shows better results overall in comparison to the other structures. This device provides [Formula: see text] S, [Formula: see text], [Formula: see text] Hz and shows strong potential to design fast electronic switches.

Parasitic Current Induced by Gate Overlap in Thin-Film Transistors.

As novel applications of oxide semiconductors are realized, various structural devices and integrated circuits are being proposed, and the gate-overlay defect phenomenon is becoming more diverse in its effects. Herein, the electrical properties of the transistor that depend on the geometry between the gate and the semiconductor layer are analyzed, and the specific phenomena associated with the degree of overlap are reproduced. In the semiconductor layer, where the gate electrode is not overlapped, it is experimentally shown that a dual current is generated, and the results of 3D simulations confirm that the magnitude of the current increases as the parasitic current moves away from the gate electrode. The generation and path of the parasitic current are then represented visually through laser-enhanced 2D transport measurements; consequently, the flow of the dual current in the transistor is verified to be induced by the electrical potential imbalance in the semiconductor active layer, where the gate electrodes do not overlap.