Gate Overlap Research Articles

A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme.

Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (BUV) exposure and backside-lift-off (BLO) schemes can not only prevent the damage when etching the source/drain (S/D) electrodes but also reduce the number of photo-masks required during fabrication and minimize the parasitic capacitance with the decreasing of gate overlap length at same time. Compared with traditional fabrication processes, the proposed process yields that thin-film transistors (TFTs) exhibit comparable field-effect mobility (9.5 cm2/V·s), threshold voltage (3.39 V), and subthreshold swing (0.3 V/decade). The delay time of an inverter fabricated using the proposed process was considerably decreased.

The effect of gate overlap on the device degradation in IGZO thin film transistors

The effect of gate overlap on the device degradation in IGZO TFTs treated by H2 and Ar plasma was experimentally investigated after positive and negative gate biases stress and hot carrier stress. Using transmission line method, the effective channel length was extracted with the length of the gate overlaps. After positive and negative biases stress, the decrease of threshold voltage shifts with the increase of the gate overlaps may be attributed to the carrier diffusion from the n− extended source and drain regions to the intrinsic channel region. The hot carrier induced threshold voltage shifts were increased with the increase of the gate overlap due to the reduction of effective channel length.

Study of RF performance of surrounding gate MOSFET with gate overlap and underlap

In this paper a simulation study is used to investigate the RF performance of surrounding gate (SRG) MOSFET. The effect of nonsymmetrical gate structure caused by non- ideality in fabrication process has also been taken care into consideration. The important RF figure-of-merits such as unity-gain cut-off frequency fT and maximum operating frequency fMAX are studied with the help of a 2D device simulator. Their trends related to the variation of different design parameters such as radius, oxide thickness, gate length, and doping along the downscaling have also been reported.

Investigation of tunnel field-effect transistors as a capacitor-less memory cell

In this work, we report experimental results on the use of tunnel field-effect transistors as capacitorless dynamic random access memory cells, implemented as double-gate fully depleted silicon-on-insulator devices. The devices have an asymmetric design, with a partial overlap of the top gate (LG) and with a total overlap of the back gate over the channel region (LG + LIN). A potential well is created by biasing the back gate (VBG) in accumulation, while the front gate (VFG) is in inversion. Holes from the p+ source are injected by the forward-biased p+ i junction and stored in the electrically induced potential well.

Current and Noise Properties of InAs Nanowire Transistors With Asymmetric Contacts Induced by Gate Overlap

Nanowire transistors are typically fabricated as geometrically symmetrical devices, with metal/semiconductor source and drain contacts rather than a graduated doping profile. While the source and drain contacts are nominally identical, contact asymmetry can arise when the gate contact is not centered over the nanowire, leaving uneven access regions with no gate coverage on one or both sides of the channel. Measuring the characteristics of devices with symmetric and asymmetric contact geometries allows contact effects to be studied. In this paper, indium arsenide nanowire transistors were fabricated with symmetric and asymmetric gate coverage. It is shown that devices with highly asymmetric gate coverage can exhibit a factor of 10 change in current and a shift in threshold of up to 0.5 V upon reversing the source-drain orientation. Devices with highly asymmetric properties show nearly identical channel-generated noise yet a significant difference in contact-generated noise levels when the contact orientation is reversed. Fully symmetric devices show higher current levels, lower threshold voltages, and lower contact-generated noise than asymmetric devices with either source or drain gated, but channel-generated noise levels are similar.

화장품 용기의 유동 특성 및 사출금형 제작에 관한 연구

화장품제조업은 동일한 제품을 대량으로 생산하고 소비되는 구조로 금형을 통한 생산은 필연적이다. 화장품을 담는 용기는 소비자의 구매의사에도 영향을 주는 요소이며 완제품가격에서 차지하는 부분이 크기 때문에 경제성, 심미성과 기능성을 충족시키는 금형이 필요하다. 화장품 용기 중에 사각형태의 용기는 미성형 불량이 다른 형태의 제품보다 자주 발생하는 특징을 가진다. 기존에 사각형 형태의 화장품용기 제작공정은 2단 금형에 사이드게이트 구조로 금형을 제작하는데 이는 후가공과 게이트 흔적이 남는 단점이 있다. 본 연구에서 제안한 오버랩게이트는 후가공이 거의 없고 음각으로 게이트가 절단되는 특징이 있으며, 사이드게이트와 비교하여 Moldflow를 이용한 유동시스템을 시뮬레이션 하였다. 오버랩게이트가 유동성, 고화, 밀도, 에어트랩 등에서 유동성 향상과 불량률을 낮출 수 있는 결과를 확인하였으며, 해석결과를 기반으로 금형을 제작을 하고 사출성형 하였다. 본 연구를 통해 미성형 불량을 줄이고 심미성, 기능성 등의 특성을 가지는 화장품용기 제품의 대량생산 가능성을 검증하였다 A cosmetic manufacturing process requires a mold that is inevitable for mass production. Cosmetic containers are one of major factors affecting the customer's purchase decision. In addition, the manufacturing cost in cosmetic container comprises a large portion of the entire product cost. Therefore, a mold satisfying the economical feasibility, aesthetics and functionality is necessary. Among the cosmetic containers, square shape containers have a tendency of having a short shot defect product. The square shaped cosmetic containers are mostly produced as a side gate shape on the two-plate molds. On the other hand, there are two disadvantages, such as gate trace and post processing requirement. The overlap-gateproposed in this study has the characteristics of intaglio gate cutting and no need for post processing. The delivery system of the overlap gate was simulated and compared with the side gate via Moldflow. The improvement in flow, frozen rate, density, and Air trap was confirmed. Based on the simulation results, the mold and performed injection molding was fabricated. In this study, the possibility of the mass production of high aesthetic and functionality cosmetic containers was verified.

Three-dimensional doping and diffusion in nano scaled devices as studied by atom probe tomography

Nowadays, technological developments towards advanced nano scale devices such as FinFETs and TFETs require a fundamental understanding of three-dimensional doping incorporation, activation and diffusion, as these details directly impact decisive parameters such as gate overlap and doping conformality and thus the device performance. Whereas novel doping methods such as plasma doping are presently exploited to meet these goals, their application needs to be coupled with new metrology approaches such as atom probe tomography, which provides the 3D-dopant distribution with atomic resolution. In order to highlight the relevant processes in terms of dopant conformality, 3D-diffusion, dopant activation and dopant clustering, in this paper we report on 3D-doping and diffusion phenomena in silicon FinFET devices. Through the use of atom probe tomography we determine the dopant distribution in a fully completed device which has been doped using the concept of self-regulatory plasma doping (SRPD). We extract the dopant conformality and spatial extent of this doping process and demonstrate that after annealing the resulting 3D-doping profiles and gate overlap are dependent on the details of the plasma doping process. We also demonstrate that the concentration-dependent 3D-diffusion process leads to concentration gradients which are different for the vertical versus the lateral direction. Through a statistical analysis of the dopant atom distributions we can identify dopant clustering in high concentration regions and correlate this with details of the dopant activation and, eventually, the device performance.

S-Parameter Characterization of Submicrometer Low-Voltage Organic Thin-Film Transistors

This letter presents the first comprehensive experimental studies on the frequency response of staggered low-voltage organic thin-film transistors (OTFTs) using S-parameter measurements. The transistors utilize air-stable dinaphtho-thieno-thiophene as the organic semiconductor with various channel lengths and gate overlaps. A peak cutoff frequency of 3.7 MHz for a channel length of 0.6 μm, gate overlap of 5 μm, and a supply voltage of 3 V is achieved. In view of the low supply voltage and air-stability, this result marks a record achievement in OTFT technology. The channel length dependence of the cutoff frequency is described in a compact model and a close correspondence to the measured data of OTFTs with variable device dimensions is shown. Moreover, the cutoff frequencies at different gate biases are found to be proportional to the dc transconductance.

The Second-Generation of HiSIM_HV Compact Models for High-Voltage MOSFETs

This paper reviews the industry-standard surface-potential-based compact model HiSIM_HV for high-voltage MOSFETs, as, e.g., the lateral double-diffused MOS transistor, and introduces important improvements implemented in the second-generation model versions (HiSIM_HV2), for which open source code has been released since October 2011. HiSIM_HV solves the Poisson equation consistently within the intrinsic MOSFET, i.e., the gate-drift overlap region and the drain-side part of the drift region. Excess carrier concentrations in the drift region are accurately considered together with the velocity saturation effect. These modeling concepts enable a scalable compact model formulation with only one internal node. Fulfillment of the current continuity between MOSFET and drift parts is required for determining the internal node potential. An important enhancement implemented in the HiSIM_HV2 models is a physically accurate compact drift region resistance model, which captures the effects of the structure-dependent 2-D current flows in overlap and drift regions with their complicated bias dependence. Furthermore, compact modeling of gate overlap capacitance, leakage currents due to, e.g., impact ionization, self-heating, noise, and symmetry properties (smooth derivatives at zero drain-source voltage) have been substantially improved.

Electrostatic Dimension of Aligned-Array Carbon Nanotube Field-Effect Transistors

Accurate electrostatics modeling of nanotubes (NTs)/nanowires (NWs) has significant implications for the ultimate scalability of aligned-array NT/NW field-effect transistors (FETs). The analysis to date has focused on limits of capacitive coupling between the 1D channel and 2D gate that is strictly relevant only in the linear response operation of NT/NW-FETs. Moreover, the techniques of electrostatic doping by independent gates that cover only part of the channel are widely used, but the nature of its electrostatic coupling has not been explored. In this paper, we use a three-dimensional, self-consistent model for NT/NW-FETs to interpret the essence of electrostatic coupling with complex configuration of electrode geometries. The interplay between 3D electric fields and its 1D termination onto the NTs/NWs suggests surprising complexity of electrostatic interaction not captured in simpler models. This coupling can change the performance metrics such as ON and OFF currents by orders of magnitude depending on (1) NT/NW density, (2) bias voltage, and (3) gate overlap length. Remarkably, this parasitic coupling persists regardless of the gate oxide thickness, changes in dielectric constant, and/or the width of the diameter distribution of NTs/NWs. The predictions of the model are systematically validated by a series of experiments.

Compact Modeling of a Generic Double-Gate MOSFET With Gate–S/D Underlap for Subthreshold Operation

In this brief, a new analytical model to compute the potential distribution in gate overlap and underlap regions of a generic double-gate (DG) MOSFET (valid for asymmetric features in front- and back-gate insulator thicknesses, gate bias, and gate work functions) for operation in the subthreshold condition is proposed. A closed form solution to 2-D Poisson's equation is obtained with approximation of parabolic potential function along vertical direction of the device. Conformal mapping technique is applied for modeling fringe electric field in the underlap regions. The proposed potential model is extended in deriving important device parameters such as threshold voltage, threshold voltage rolloff, DIBL, subthreshold swing, etc. Model predictions demonstrate that significant improvement in subthreshold operation can be achieved with 4T asymmetric underlap DG MOSFETs in comparison to 3T symmetric nonunderlap DG MOSFETs.

An Experimental Study of the Effects of Source/Drain to Gate Overlap in Pentacene Thin-Film Transistors

The effects of the source/drain (S/D) to gate overlap on the electrical characteristics of pentacene organic thin-film transistors (OTFTs) are reported. The S/D to gate overlap dimension was varied by adjusting the gate width, while the channel length and width were fixed. The threshold voltage was found to decrease on increasing the overlap dimension; in contrast, the field-effect mobility increased. These characteristic variations are explained on aspects of charge injection and transport properties in pentacene OTFTs, due to the presence of S/D to gate overlaps. The results demonstrate the significant effect of the overlap on the OTFT performance.

An Experimental Study of the Effects of Source/Drain to Gate Overlap in Pentacene Thin-Film Transistors

The effects of the source/drain (S/D) to gate overlap on the electrical characteristics of pentacene organic thin-film transistors (OTFTs) are reported. The S/D to gate overlap dimension was varied by adjusting the gate width, while the channel length and width were fixed. The threshold voltage was found to decrease on increasing the overlap dimension; in contrast, the field-effect mobility increased. These characteristic variations are explained on aspects of charge injection and transport properties in pentacene OTFTs, due to the presence of S/D to gate overlaps. The results demonstrate the significant effect of the overlap on the OTFT performance.

Scaling behaviour of a-IGZO TFTs with transparent a-IZO source/drain electrodes

We analysed the scaling behaviour of amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) with amorphous indium zinc oxide (a-IZO) transparent source/drain (S/D) electrodes. Due to the sputtering damage of the back-channel region during the a-IZO deposition process, the output characteristics show early saturation behaviour and the field-effect mobility in the saturation region is severely decreased in comparison with that in the linear region, especially when the channel length is decreased. Based on the transmission line method, we found that a long gate overlap distance is required due to the long current transfer length. Therefore, optimizing the parasitic resistance is required for the scaling down of a-IGZO TFTs with transparent a-IZO S/D electrodes.

An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance

In this paper fringe capacitance of double hetero gate Tunnel FET has been studied. The physical model for fringe capacitance is derived considering source gate overlap and gate drain non overlap. Inerface trap charge and oxide charges are also introduced under positive bias stress and hot carrier stress and their effect on fringe capacitance is also studied. The fringe capacitance is significant speed limiter in Double gate technology. The model is tested by comparing with simulation results obtained from Sentauras TCAD simulations .

CAVET on Bulk GaN Substrates Achieved With MBE-Regrown AlGaN/GaN Layers to Suppress Dispersion

A current aperture vertical electron transistor (CAVET) with a Mg-ion-implanted current blocking layer (CBL) and a channel regrown by plasma assisted molecular beam epitaxy (MBE), is successfully demonstrated on bulk GaN to work as a high voltage device. The fabrication of the device combined a drift region grown by metalorganic chemical vapor deposition (MOCVD), to hold the blocking voltage, with AlGaN/GaN layers regrown by plasma-MBE to conduct current. The device registered a maximum current of 4 kA· cm-2 under direct-current operation offering a specific on-state resistance Ron - A of 2.2 mΩ·cm2. With 80 μs pulses applied to the gate, the devices showed no dispersion. The increased aperture length Lap resulted in the decrease in specific Ron, as expected. The impact of the gate overlap to aperture Lgo on the leakage current was studied, where the leakage current was found to increase with a smaller overlap.

Quasi-2-Dimensional Compact Resistor Model for the Drift Region in High-Voltage LDMOS Devices

High-voltage (HV) metal-oxide-semiconductor field-effect transistors (MOSFETs) of the laterally diffused metal-oxide-semiconductor (LDMOS) type enable applications over a wide range of bias voltages by optimizing the combined structure of MOSFET and drift region at its drain side. We report a physically accurate compact resistor model of the LDMOS drift region, adapted to the special requirements of the combined structure with a MOSFET. In particular, the reported resistor model captures the effects of the 2-D current flow in the drift region with its complicated bias dependence. The resistor model considers two device-structure-dependent potentials, namely, the internal node potential within the highly resistive drift region and the potential underneath the gate overlap region. The consistent potential-based description over the complete LDMOS device is the key modeling technology for enabling the accurate reproduction of the bias-dependent 2-D current flow and the resulting <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> characteristics for a wide range of structure variations with a small number of only six fitting parameters. The reported quasi-2-D resistor model is implemented in the second-generation Hiroshima-university STARC IGFET Model-High Voltage (HiSIM-HV) compact models for HV MOSFETs and is expected to be useful for both, optimization of LDMOS circuits and devices.

Observation of diameter dependent carrier distribution in nanowire-based transistors

The successful implementation of nanowire (NW) based field-effect transistors (FET)critically depends on quantitative information about the carrier distribution inside suchdevices. Therefore, we have developed a method based on high-vacuum scanning spreadingresistance microscopy (HV-SSRM) which allows two-dimensional (2D) quantitative carrierprofiling of fully integrated silicon NW-based tunnel-FETs (TFETs) with 2 nm spatialresolution. The key elements of our characterization procedure are optimized NWcleaving and polishing steps, the use of in-house fabricated ultra-sharp diamond tips,measurements in high vacuum and a dedicated quantification procedure accounting for theSchottky-like tip–sample contact affected by surface states. In the case of the implantedTFET source regions we find a strong NW diameter dependence of conformality,junction abruptness and gate overlap, quantitatively in agreement with processsimulations. In contrast, the arsenic doped drain regions reveal an unexpectedNW diameter dependent dopant deactivation. The observed lower drain dopingfor smaller diameters is reflected in the device characteristics by lower TFEToff-currents, as measured experimentally and confirmed by device simulations.

Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor

A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.

Distribution of post-breakdown resistance of MOSTFETs

In this paper, a post-breakdown resistance value of antifuse cells has been calculated with respect to breakdown spots. Also, the effect of body doping concentration and source/drain abruptness on the post-breakdown resistance has been observed in the case of gate underlap and overlap structures. Based on simulation results, we have proposed some ways of making the post-breakdown resistance distribution uniform.