The effect of gate overlap on the device degradation in IGZO thin film transistors

Abstract

The effect of gate overlap on the device degradation in IGZO TFTs treated by H2 and Ar plasma was experimentally investigated after positive and negative gate biases stress and hot carrier stress. Using transmission line method, the effective channel length was extracted with the length of the gate overlaps. After positive and negative biases stress, the decrease of threshold voltage shifts with the increase of the gate overlaps may be attributed to the carrier diffusion from the n− extended source and drain regions to the intrinsic channel region. The hot carrier induced threshold voltage shifts were increased with the increase of the gate overlap due to the reduction of effective channel length.