Abstract
Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (BUV) exposure and backside-lift-off (BLO) schemes can not only prevent the damage when etching the source/drain (S/D) electrodes but also reduce the number of photo-masks required during fabrication and minimize the parasitic capacitance with the decreasing of gate overlap length at same time. Compared with traditional fabrication processes, the proposed process yields that thin-film transistors (TFTs) exhibit comparable field-effect mobility (9.5 cm2/V·s), threshold voltage (3.39 V), and subthreshold swing (0.3 V/decade). The delay time of an inverter fabricated using the proposed process was considerably decreased.
Highlights
Numerous recent studies have focused on oxide semiconductors, such as amorphous indium–gallium–zinc oxide (a-IGZO)
The a-IGZO thin-film transistors (TFTs) that are employed in displays are typically fabricated using back-channel-etching structure and five photomasks, including the definition of an etching-stop (ES) layer to protect the a-IGZO active layer from damage caused by etching the source/drain (S/D) electrodes [8]
A new two-photo-mask process with continuous-etching scheme was proposed for fabricating a-IGZO TFTs that exhibit self-aligned structures without ES layers
Summary
Numerous recent studies have focused on oxide semiconductors, such as amorphous indium–gallium–zinc oxide (a-IGZO) Because of their high mobility and transparency, these semiconductors have been applied as active channel layers in thin-film transistors (TFTs) [1,2,3]. The a-IGZO TFTs that are employed in displays are typically fabricated using back-channel-etching structure and five photomasks, including the definition of an etching-stop (ES) layer to protect the a-IGZO active layer from damage caused by etching the source/drain (S/D) electrodes [8]. To reduce the fabrication costs and prevent hydrogen-based material from affecting the a-IGZO active layer during ES deposition [11], Uhm et al proposed a two-photo-mask scheme that employed a gray-tone photomask to fabricate TFT devices [12]; the lack of an ES layer can cause damage to the a-IGZO active island when etching the S/D electrodes.
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