Abstract
In this paper fringe capacitance of double hetero gate Tunnel FET has been studied. The physical model for fringe capacitance is derived considering source gate overlap and gate drain non overlap. Inerface trap charge and oxide charges are also introduced under positive bias stress and hot carrier stress and their effect on fringe capacitance is also studied. The fringe capacitance is significant speed limiter in Double gate technology. The model is tested by comparing with simulation results obtained from Sentauras TCAD simulations .
Highlights
As MOSFETs are scaled to nanometer dimensions, various short channel effects such as DIBL, VT roll-off, sub 60mV/decade subthreshold swing etc are coming into picture
Problems like threshold voltage shift caused by hot carrier injection, non-rail to rail voltage swings, and high operating voltage requirements will arise in Impact ionization MOSFETS [2]
Since tunnel FET operation is completely different from MOSFET, the derivations for inner and outer fringe capacitance is different
Summary
As MOSFETs are scaled to nanometer dimensions, various short channel effects such as DIBL, VT roll-off, sub 60mV/decade subthreshold swing etc are coming into picture. To overcome short channel effects, one needs to design a device which uses other mode of carrier transport so that a lower subthreshold swing can be achieved. Problems like threshold voltage shift caused by hot carrier injection, non-rail to rail voltage swings, and high operating voltage requirements will arise in Impact ionization MOSFETS [2]. Since tunnel FET operation is completely different from MOSFET, the derivations for inner and outer fringe capacitance is different. The inner and outer components of parasitic fringe capacitance is modelled for tunnel FET. We report first time the effect of positive bias stress and hot carrier stress on the fringe capacitor of double hetero gate tunnel FET. The oxide charge is dominant in case of hot carrier stress and the interface traps are dominant in case of positive bias stress [11]
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: International Journal of VLSI Design & Communication Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
