Gate Lag Research Articles

Thin channel Ga2O3 MOSFET with 55 GHz fMAX and >100 V breakdown

This Letter reports a highly scaled 90 nm gate length β-Ga2O3 (Ga2O3) T-gate MOSFET with a power gain cutoff frequency (fMAX) of 55 GHz. The 60 nm thin epitaxial Ga2O3 channel layer was grown by molecular beam epitaxy, while the highly doped (n++) source/drain regions were regrown using metal organic chemical vapor deposition. Maximum on current (IDS,MAX) of 160 mA/mm and trans-conductance (gm) around 36 mS/mm were measured at VDS = 10 V for LSD = 1.5 μm device. Transconductance and on current are limited by high channel sheet resistance (Rsheet). Gate/drain breakdown voltage of 125 V was measured for LGD = 1.2 μm. We extracted 27 GHz current gain cutoff frequency (fT) and 55 GHz fMAX for 20 V drain bias for unpassivated devices. While no current collapse was seen initially for both drain and gate lag measurements for 500 ns pulse, moderate current collapse was observed after DC, RF measurements caused by electrical stressing. We calculated a high fT. VBR product of 3.375 THz V, which is comparable to the state-of-the-art GaN HEMTs. This figure of merit suggests that Ga2O3 could be a potential candidate for X-band application.

Fabrication of recessed-gate AlGaN/GaN MOSFETs using TMAH wet etching with Cu ion implantation

In this study, recessed-gate AlGaN/GaN MOSFETs were fabricated using a novel recess etching method––TMAH wet etching with Cu ion implantation. This innovative approach injects Cu ions selectively into the target AlGaN layer, creating defects that are then etched with a TMAH solution, dissolving Ga along with the defect. Compared to the conventional GaN recess etching method of ICP-RIE dry etching, TMAH wet etching offers more precise etching without causing plasma damage on the etched surface. To demonstrate the superiority of TMAH wet etching, devices fabricated with this method were analyzed and compared with devices fabricated using ICP-RIE dry etching. The AFM images of the etched surface demonstrated the superior stability of TMAH wet etching. In addition, electrical characteristics measurements revealed that the devices using TMAH wet etching exhibited a higher on-current (295.05 mA/mm), lower gate lag rate (15.98 %), and a higher breakdown voltage (733 V) than ICP-RIE etched devices.

Experimentally Validated Gate-Lag Simulations of AlGaN/GaN HEMTs Using Fermi Kinetics Transport

This article presents for the first time a direct connection between gate lag observed in drain current transient measurements of gallium nitride (GaN) high-electron-mobility transistors (HEMTs) and traps located in the barrier of the transistor epitaxy. Semiclassical numerical simulations are presented using the Air Force Research Laboratory’s (AFRL’s) Fermi kinetics transport (FKT) solver and are validated with drain current transient measurements. Capacitance–voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C} - {V}$ </tex-math></inline-formula> ) and conductance–voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${G} - {V}$ </tex-math></inline-formula> ) measurements are also presented to provide further insights into the trap location used in the FKT simulations. These simulations indicate that equivalent defects located specifically at the AlGaN barrier/GaN cap interface of an AFRL GaN HEMT with a density of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.5\times 10^{{12}}$ </tex-math></inline-formula> cm−2 and positioned 1.464 eV below the GaN cap conduction band edge were the salient traps linked to the gate-lag phenomenon. The study highlights the importance of experimentally benchmarked device simulation for trapping analysis in GaN HEMTs and may provide significant insights into device engineers for mitigating trapping effects in state-of-the-art GaN technologies.

Reliability, Applications and Challenges of GaN HEMT Technology for Modern Power Devices: A Review

A new generation of high-efficiency power devices is being developed using wide bandgap (WBG) semiconductors, like GaN and SiC, which are emerging as attractive alternatives to silicon. The recent interest in GaN has been piqued by its excellent material characteristics, including its high critical electric field, high saturation velocity, high electron mobility, and outstanding thermal stability. Therefore, the superior performance is represented by GaN-based high electron mobility transistor (HEMT) devices. They can perform at higher currents, voltages, temperatures, and frequencies, making them suitable devices for the next generation of high-efficiency power converter applications, including electric vehicles, phone chargers, renewable energy, and data centers. Thus, this review article will provide a basic overview of the various technological and scientific elements of the current GaN HEMTs technology. First, the present advancements in the GaN market and its primary application areas are briefly summarized. After that, the GaN is compared with other devices, and the GaN HEMT device’s operational material properties with different heterostructures are discussed. Then, the normally-off GaN HEMT technology with their different types are considered, especially on the recessed gate metal insulator semiconductor high electron mobility transistor (MISHEMT) and p-GaN. Hereafter, this review also discusses the reliability concerns of the GaN HEMT which are caused by trap effects like a drain, gate lag, and current collapse with numerous types of degradation. Eventually, the breakdown voltage of the GaN HEMT with some challenges has been studied.

Trapping Effect in AlInN/GaN HEMTs: A Study Based on Photoionization and Pulsed Electrical Measurements

The aim of this article is to detect electron traps in AlInN/GaN transistors operating at room temperature by combining pulsed electrical measurement with photoionization techniques to rapidly assess their activation energies and time constants. In addition, this technique can also reveal the presence of electron traps that cannot be observed by using pulsed measurements alone. Thus, two electron traps were identified including a deep level whose origin could be related to dislocations in the GaN buffer existing in the devices. At the same time, this study has shown that the time constants of these electron traps are inferior to 400 ns and that the electrical behavior of the components is also degraded by the presence of surface states with a time constant of 4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> . Moreover, these two traps are at the origin of the gate lag effects observed during the pulsed electrical characterization of the AlInN/GaN high electron mobility transistors (HEMTs). Likewise, a negative output conductance induced by a trapping effect has been put forward.

The DC Performance and RF Characteristics of GaN-Based HEMTs Improvement Using Graded AlGaN Back Barrier and Fe/C Co-Doped Buffer

In this article, the impact of the graded AlGaN back barrier and Fe\C co-doping buffer structure on the AlGaN <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$/$ </tex-math></inline-formula> GaN high electron mobility transistors (HEMTs) is proposed and systematically investigated. Due to effective suppression of Fe tail in unintentionally doped GaN (uid-GaN) layer by the insertion of the thick graded AlGaN back barrier layer, a large maximum drain current density and a transconductance peak are achieved. Meanwhile, the breakdown voltage is significantly improved by the use of Fe\C co-doping GaN buffer design. More importantly, it is revealed that the graded-AlGaN design can reduce the range and intensity of the electrical potential distribution in uid-GaN layer and then effectively suppress the acceptor-induced trapping\detrapping effect under high drain voltage. The RF small-signal performance of Fe-doped GaN (GaN:Fe)\C co-doping buffer HEMT exhibits significant improvement. In addition, load-pull measurement at 8 GHz revealed that a saturation power increases from 38.04 to 41.07 dB, a power gain increases from 9.06 to 10.58 dB, and an associate power-added-efficiency (PAE) increased from 40.27% to 50.18%. Our proposed GaN-based epitaxial structure can not only suppress the gate lag by reduce AlGaN surface electric field, but it can also suppress the drain lag by reduce the amplitude and range of potential distribution. It indicates that our proposed device has great potential for future high-voltage RF power amplifier application.

Analysis of Hot Carrier Degradation in 0.25-μm Schottky Gate AlGaN/GaN HEMTs

In this work, we report hot carrier-induced degradation in normally-on AlGaN/GaN high electron mobility transistors (HEMTs) with a 0.25-μm gate. To analyze the hot carrier effect, the semi-on state stress test was carried out and the DC and pulsed I-V characteristics were analyzed. The stress condition was set at the gate voltage of -3.8 V and the drain voltage of 40 V, where the drain current was at 10% of the maximum. After a stress test, the positive shift of the threshold voltage was observed and the drain current was decreased by 19%. In addition, the gate and drain lag phenomena were pronounced when measured by the pulse with a 1.23% duty cycle. The device degradation can be attributed to the hot electron-induced trapping during the semi-on stress test, which imposed the high electric field and the low channel temperature in the device.

Hole Injection Effect and Dynamic Characteristic Analysis of Normally Off p-GaN HEMT with AlGaN Cap Layer on Low-Resistivity SiC Substrate.

A p-GaN HEMT with an AlGaN cap layer was grown on a low resistance SiC substrate. The AlGaN cap layer had a wide band gap which can effectively suppress hole injection and improve gate reliability. In addition, we selected a 0° angle and low resistance SiC substrate which not only substantially reduced the number of lattice dislocation defects caused by the heterogeneous junction but also greatly reduced the overall cost. The device exhibited a favorable gate voltage swing of 18.5 V (@IGS = 1 mA/mm) and an off-state breakdown voltage of 763 V. The device dynamic characteristics and hole injection behavior were analyzed using a pulse measurement system, and Ron was found to increase and VTH to shift under the gate lag effect.

Analysis of slow-current transients or current collapse in AlGaN/GaN HEMTs with field plate and high-k passivation layer

We study how the dielectric constant of passivation layer εr and field-plate related parameters (its length LFP, passivation-layer thickness Ti) affect the reduction rates of drain current arising from drain lag, gate lag and current collapse in AlGaN/GaN HEMTs. We plot the current-reduction rates versus Ti for different εr. It is indicated that depending on εr, the drain-lag and current-collapse rates take minimum at certain Ti. When εr is 7, 20, 30 and 50, the current-reduction rates become minimum at Ti = 0.03, 0.1, 0.1, and 0.2 μm, respectively. Hence, at the minimum point, εr/Ti which is proportional to capacitance of the passivation layer takes a nearly constant value at 250 ± 50/μm. At this value of Ti, the lags and current collapse are reduced when LFP becomes long for every εr considered here.

Temperature dependent pulsed IV and RF characterization of β-(AlxGa1−x)2O3/Ga2O3 hetero-structure FET with ex situ passivation

In this work, we report a study of the temperature dependent pulsed current voltage and RF characterization of β-(AlxGa1−x)2O3/Ga2O3 hetero-structure FETs (HFETs) before and after silicon nitride (Si3N4) passivation. Under sub-microsecond pulsing, a moderate DC-RF dispersion (current collapse) is observed before passivation in gate lag measurements, while no current collapse is observed in the drain lag measurements. The dispersion in the gate lag is possibly attributed to interface traps in the gate–drain access region. DC-RF dispersion did not show any strong dependence on the pulse widths. Temperature dependent RF measurements up to 250 °C do not show degradation in the cutoff frequencies. After Si3N4 deposition at 350 °C, a shift of the threshold voltage is observed which changed the DC characteristics. However, the current collapse is eliminated; at 200 ns pulse widths, a 50% higher current is observed compared to the DC at high drain voltages. No current collapse is observed even at higher temperatures. RF performance of the passivated devices does not show degradation. These results show that ex situ deposited Si3N4 is a potential candidate for passivation of β-(AlxGa1−x)2O3/Ga2O3 HFETs.

Temperature-Dependent Current Dispersion Study inβ-Ga₂O₃ FETs Using Submicrosecond Pulsed I–V Characteristics

A comprehensive study of drain current dispersion effects in β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> field-effect transistors (FETs) has been done using dc and pulsed measurements. Both the virtual gate effect in the gate-drain access region and mobile traps under the gate are the most plausible explanations for the experimentally observed pulsed current dispersion and high-temperature threshold voltage shift, respectively. Unpassivated devices show significant current dispersion between dc and pulsed I- V response in gate lag measurements characterized by time constants in the range of 400-690 μs both at room temperature and higher temperatures. The increasing time constant with temperature suggests a complex electron capture and emission process in the virtual gate. The reactive ion etching step during the device fabrication is most likely responsible for introducing the traps. The effect of traps can be minimized by using surface passivation layers, in this case, silicon nitride, which shows significant improvement in the current dispersion. This work demonstrates the detrimental effect that the traps can have on the current dispersion, which significantly limits the high-frequency operation of the device.

Hydrogen-Related Recovery Effect of AlGaN/GaN High-Electron-Mobility Transistors Irradiated by High-Fluence Protons

The related recovery effect of hydrogen on AlGaN/gallium nitride (GaN) high-electron-mobility transistors (HEMTs) irradiated by high-fluence protons was investigated in this article. The results show that under the same temperature and time conditions, the recovery effect induced by thermal hydrogen annealing is better than that of ordinary thermal annealing. Compared with the ordinary thermal annealing, the high-fluence proton-irradiated device experienced a 65-mA additional increase in saturation current at the gate-to-source voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> ) of 0 V, a 0.074-V additional negative shift of the threshold voltage, a more significant increase in reverse gate leakage current and better gate lag after the hydrogen treatment. The defect densities are extracted by the low-frequency noise method. It shows that the trap density decreases from 8.32 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">17</sup> to 6.84 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">17</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> ·eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> after ordinary thermal annealing and then decreases from 6.84 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">17</sup> to 3.85 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">17</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> ·eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> after hydrogen treatment of an irradiated AlGaN/GaN HEMT. The mechanism for the decrease of trap density after the hydrogen treatment could be attributed to the H-passivated defects in the structures of AlGaN/GaN HEMTs.

Look-up table based I-V model for GaN HEMT devices for Microwave Applications

In this work, a newly found innovative interposable lookup table based nonlinear empirical DC I-V model for GaN HEMT device has been formulated. Angelov and Yang's models have been taken as reference models to study the effects of bias (Vgs, Vds) dependent traps (gate lag and drain lag), self-healing, virtual gate formation, etc. on I-V characteristics functions and their inclusion into I-V equation functions of the proposed model. A new polynomial ratio function of Vds with its coefficients varying with Vgs has been formulated as a first function of the I-V model equation, to describe the transfer characteristics of the GaN HEMT. The obtained coefficients of the polynomial ratio function have been calculated by the curve fitting tool, are used to form a look-up table so that the I-V model is fast and accurate. Model verification has been done using 8 × 75 µm gate periphery and 0.25 µm gate length GaN HEMT of UMS foundry. The measured and modeled results of I-V characteristics as well as transfer characteristics are compared and found to be matched accurately with each other. Because of this, this model is more accurate and proficient in the representation of GaN HEMT I-V characteristics when compared to the Angelov DC I-V model. The proposed methodology can be used to model all GaN HEMT devices.Using the proposed nonlinear I-V equation, an empirical model has been generated in AWR MWO using an interpolable lookup table of coefficients varying with Vgs for the GaN HEMT of UMS, CREE and WIN foundry, which can be used for Computer-Aided Design (CAD) of RF circuits, etc.

Trapping effects on AlGaN/GaN HEMT characteristics

This paper describes device simulation studies of surface and buffer trapping effects on static I-V, output-admittance (Y22), and transient characteristics of AlGaN/GaN HEMTs. The TCAD simulation model considering surface donors at EC − 0.5 eV and buffer traps at EC − 0.47 eV have been used to quantitatively reproduce the measured DC, Y22 frequency dispersion, gate-lag (GL) and drain-lag (DL) transients of AlGaN/GaN HEMT with 0.25 µm gate length. Moreover, simulated GL and DL transient responses of AlGaN/GaN HEMT with a longer gate length (0.5 µm) are validated with the reported experimental results. The impact of barrier trap at EC − 0.45 eV on the HEMT properties is also explored. It is shown that by matching simulation results with experimental data, it is possible to identify the trap (surface or buffer) responsible for a particular trapping induced degradation as well as its concentration and capture cross-section.

High temperature operation to 500 °C of AlGaN graded polarization-doped field-effect transistors

AlGaN polarization-doped field-effect transistors were characterized by DC and pulsed measurements from room temperature to 500 °C in ambient. DC current-voltage characteristics demonstrated only a 70% reduction in on-state current from 25 to 500 °C and full gate modulation, regardless of the operating temperature. Near ideal gate lag measurement was realized across the temperature range that is indicative of a high-quality substrate and sufficient surface passivation. The ability for operation at high temperature is enabled by the high Schottky barrier height from the Ni/Au gate contact, with values of 2.05 and 2.76 eV at 25 and 500 °C, respectively. The high barrier height due to the insulatorlike aluminum nitride layer leads to an ION/IOFF ratio of 1.5 × 109 and 6 × 103 at room temperature and 500 °C, respectively. Transmission electron microscopy was used to confirm the stability of the heterostructure even after an extended high-temperature operation with only minor interdiffusion of the Ni/Au Schottky contact. The use of refractory metals in all contacts will be key to ensure a stable extended high-temperature operation.

Alpha Particle Irradiation of High Aluminum Content AlGan Polarization Doped Field Effect Transistors

Alpha particle irradiation at 18 MeV was performed on high aluminum content AlGaN Polarization Doped Field Effect Transistors (POLFTs) and characterized by DC and switching measurements. The POLFETs underwent a reduction in DC saturation current of 23% and 33% at fluences of 1 × 1013 cm−2 and 3 × 1013 cm−2, respectively. Carrier removal rates in the range of 2520 cm−1 and 7100 cm−1 were observed, which are similar to previously reported values for GaN HEMTs. The POLFETs under 100 kHz gate lag measurement demonstrated zero degradation while compared to a traditional GaN HEMT device which suffered serious current collapse as a result of formation of a virtual gate from radiation-induced defects.

Mechanisms of a Rectifying TiN Gate Contact for AlGaN$/$GaN HEMTs on Silicon Substrate

Rectifying Titanium Nitride (TiN) gate contact technology is developed for AlGaN $/$ GaN based micro and nanometer HEMTs. A high compressive strain occurring in thinner TiN films (ranging from 5 nm to 60 nm), deposited by sputtering, leads to a reduction in tensile strain at the surface of AlGaN barrier. The diminution in tensile strain forms a pseudo- $p$ -type layer (diode-like). This strain reduction has no effect on the bandgap of the AlGaN barrier layer, allowing the gate to withstand a reverse gate bias larger than 100 V. Characterization using the high-resolution transmission electron microscopy combined with the X-ray photoelectron spectroscopy reveals a good TiN $/$ AlGaN interface quality and no diffusion of TiN into AlGaN. The effective energy barrier of the rectifying nanoscale TiN gate contact has a relatively large height of 1.1 eV associated with an ideality factor of 1.4. A dramatic drop of the reverse-bias leakage current down to 11 pA $/$ mm is measured at −30 V. In addition, electrical measurements show very low gate and drain lag effects of 4.2 ${\%}$ and 6.7 ${\%}$ , respectively.

Comparative study of Au and Ni/Au gated AlGaN/GaN high electron mobility transistors

This paper presents the electrical comparison of Au and Ni/Au gated HEMT devices and diodes. Au Schottky diodes on an AlGaN/GaN heterostructure exhibit better electrical performance in comparison to conventional Ni/Au diodes with an improved Schottky barrier height (SBH) and lower reverse leakage current. The SBH extracted from I-V for Au and Ni/Au is 1.29 eV and 0.74 eV, respectively. Au Schottky contacts on GaN have a better ideality factor of 1.55 than Ni, which is 1.61. Capacitance-voltage measurement revealed a positive shift in threshold voltage in the case of Au diodes with a reduced capacitance value with respect to Ni/Au diodes. This decrease in threshold and capacitance indicates a decrease in the 2DEG carrier concentration. The decrease in the 2DEG carrier concentration is consistent with three terminal device measurements. Despite a small decrease in drain current (8%), the Au gated HEMT devices have shown an improved subthreshold slope (13%) and nearly 4 order improvement in the ION/IOFF ratio than Ni/Au gated HEMTs. Pulse IV characterization has indicated that gate lag and drain lag have no major changes with respect to gate metal, whereas current collapse increases for high work function metals.

Extreme Temperature Operation of Ultra-Wide Bandgap AlGaN High Electron Mobility Transistors

High Aluminum content channel (Al0.85Ga0.15N/ Al0.7Ga0.3N) High Electron Mobility Transistors (HEMTs) were operated from room temperature to 500°C in ambient. The devices exhibited only moderate reduction, 58%, in on-state forward current. Gate lag measurements at 100 kHz and 10% duty only showed a slight reduction in pulsed current from DC at 500°C and high gate voltages. Interfacial trap densities were $2 \times 10^{11}$ over the range 25–300°C and $3 \times 10^{12}$ cm $^{-2}$ from 300–500°C from the subthreshold swing. These low interfacial trap densities and the near ideal gate lag measurement indicate high-quality epi layers. The insulating properties of the barrier layer led to low gate induced drain leakage current of $\sim 10^{-12}$ A/mm and $\sim 10^{-8}$ A/mm at 25 and 500°C, respectively. Low leakage current was enabled by the high Schottky barrier of the Ni/Au gate, 1.1 eV and 3.3 eV at 25 and 500°C, respectively. These properties of the AlGaN channel HEMTs demonstrate their potential for high power and high temperature operation.

Improvement in DC and pulse characteristics of AlGaN/GaN HEMT by employing dual metal gate structure

This paper presents the fabrication and electrical characterization of dual metal gated high electron mobility transistors (DMG-HEMTs) on AlGaN/GaN/SiC hetero-structure using oblique and normal angle deposition of Nickel and Titanium respectively as gate metals. A noteworthy advance in the device characteristics has been achieved including DC and pulse drain current, transconductance, ON-resistance. The upsurge in DC drain current and transconductance is ∼8% and 11% respectively. Pulse I–V measurements have been executed to evaluate the dynamic performance of DMG-HEMTs. Pulse I–V unveils significant improvement in drain lag, gate lag and current collapse in these devices which is due to the redistribution of electric field under the gate.