Gate Lag Research Articles

A New 4H-SiC MESFET Utilizing N<sup>-</sup> Shielding and Field Plate Techniques Simultaneously

Some new techniques include n- shielding, buried channel and field plate are firstly adopted together for design and fabrication of 4H-SiC microwave MESFETs. The testing results show that a relatively broad and uniform transconductance versus gate voltage was obtained using a 0.1m n- shielding. 0.3mm gate periphery device shows good DC and RF performance such as 5.27W/mm power density, 6.7dB power gain and 43% power added efficiency at 2.3GHz under pulse operation. Compared to conventional SiC MESFETs, a gate lag ratio as high as 0.84 can be achieved for the developed devices even under a nearly actual operating condition.

Buffer‐trap and surface‐state effects on gate lag in AlGaN/GaN HEMTs

AbstractTwo‐dimensional simulation of turn‐on characteristics of Al‐GaN/GaN HEMTs is performed in which both buffer traps and surface states are considered. It is studied how the so‐called gate lag is affected by these factors. It is shown that gate lag due to buffer traps can occur because in the off state where the gate voltage is negative, electrons are injected into the buffer layer and captured by the traps, leading to more negatively charged buffer layer. It is also shown that gate lag due to an electron‐trap‐type surface state can occur only when electron's gate tunneling is considered (© 2010 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Carrier velocity in InAlN/AlN/GaN heterostructure field effect transistors on Fe-doped bulk GaN substrates

We report microwave characteristics of field effect transistors employing InAlN/AlN/GaN heterostructures grown on low-defect-density bulk Fe-doped GaN substrates. We achieved unity current gain cutoff frequencies of 14.3 and 23.7 GHz for devices with gate lengths of 1 and 0.65 μm, respectively. Measurements as a function of applied bias allow us to estimate the average carrier velocity in the channel to be ∼1.0×107 cm/sec for a 1 μm device. Additionally, we found nearly no gate lag in the devices, which is considered a precondition for good performance under large signal operation.

Effect of lattice mismatch on gate lag in high quality InAlN/AlN/GaN HFET structures

AbstractGrown lattice matched to GaN, InAlN‐based heterojunction field effect transistors (HFETs) are promising due to the relatively large band discontinuity at the interface and lack of misfit strain. Despite the recent progress in the growth, there still exists some questions as to the true lattice matching condition of InAlN to GaN due to discrepancies in the value of the lattice parameters of the InN binary, as well as the literature value of the InAlN bowing parameters. In order to address this, we used the gate lag as a supplementary measurement to verify lattice matching to the underlying GaN, as strain‐free layers would not have piezoelectric charge at the surface, which would be one source of lag. We observe very low lag for a nearly lattice matched barrier, and a marked increase as the composition deviates from the lattice matched condition. Additionally, FETs fabricated on a nearly matched layer boast a maximum drain current of over 1.5 and ∼2.0 A/mm and transconductances of ∼275 and ∼300 mS/mm at DC and in pulsed modes, respectively, and a cutoff frequency of 15.9 GHz (an fT*LG product of 10.3) for a gate length of 0.65 µm.

Square-Gate AlGaN/GaN HEMTs With Improved Trap-Related Characteristics

In this brief, the trap-related characteristics of high-breakdown AlGaN/GaN high-electron-mobility transistors (HEMTs) were investigated. Compared with a conventional multifinger layout, the square-gate design presented reduced the current collapse from 19% to 6% and almost eliminated the gate lag. The flicker noise density and the gate leakage decreased from 1.16 times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> to 1.17 times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-11</sup> 1/Hz ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> = 100 Hz) and from 7.36 times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> to 1.80 times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> A/mm ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = -4 V and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 100 V), respectively. The breakdown voltage was also improved from 350 to 650 V. With the channel area away from the defects generated by the mesa etching process, the square-gate AlGaN/GaN HEMTs demonstrated excellent performance with much less trapping effects.

Characterisation and modelling of parasitic effects and failure mechanisms in AlGaN/GaN HEMTs

This work is a study of the degradations of AlGaN/GaN HEMTs induced by 2000 h of ageing tests. The methodology is based on cross-characterisation analysis. The life tests (HTO 150 °C, HTO 175 °C and HTRB 175 °C and Idq 90 °C) have mainly induced a decrease of the saturation drain current, occurring during the first 50 h, followed by a stabilisation. There is a shift of the pinch-off voltage in the range of 0.1–0.2 V while the Schottky contact is rather stable after ageing. The evolution of the electrical characteristics after ageing does not depend on the bias conditions but rather more on the channel temperature. It seems to be neither field nor current driven. Low frequency drain current noise demonstrates that there is no trap creation and the weak evolution of the 1/ f noise confirms that there is no degradation in the channel. Moreover, pulsed I– V measurements show a weak evolution of gate lag and drain lag rates after ageing. The same degradation mode is demonstrated for all life tests with rather high activation energy of 1.6 eV. The weak evolution of electrical characteristics observed during the life tests cannot be obviously explained by a single physical mechanism and results from a combination of trap-related effects before stabilisation.

Analysis of field-plate effects on buffer-related lag phenomena and current collapse in GaN MESFETs and AlGaN/GaN HEMTs

A two-dimensional transient analysis of field-plate GaN MESFETs and AlGaN/GaN HEMTs is performed in which a deep donor and a deep acceptor are considered in a semi-insulating buffer layer, and quasi-pulsed current–voltage curves are derived from them. How the existence of a field plate affects buffer-related drain lag, gate lag and current collapse is studied. It is shown that in both MESFET and HEMT, the drain lag is reduced by introducing a field plate because electron injection into the buffer layer is weakened by it, and the buffer-trapping effects are reduced. It is also shown that the field plate could reduce buffer-related current collapse and gate lag in the FETs. The dependence of lag phenomena and current collapse on the field-plate length and on the SiN passivation layer thickness is also studied. The work suggests that in the field-plate structures, there is an optimum thickness of the SiN layer to minimize the buffer-related current collapse and drain lag in GaN MESFETs and AlGaN/GaN HEMTs.

Reduction of buffer‐related current collapse in field‐plate AlGaN/GaN HEMTs

AbstractTwo‐dimensional transient analyses of field‐plate AlGaN/GaN HEMTs are performed in which a deep donor and a deep acceptor are considered in a semi‐insulating buffer layer, and quasi‐pulsed current‐voltage curves are derived from them. It is studied how the existence of field plate affects buffer‐related drain lag, gate lag and current collapse. It is shown that the drain lag is reduced by introducing a field plate, because electron injection into the buffer layer is weakened by it, and the trapping effects are reduced. It is also shown that the current collapse and gate lag are reduced in the field‐plate structure. The dependence on SiN passivation layer thickness is also studied, suggesting that there is an optimum thickness of SiN layer to minimize the buffer‐related current collapse and drain lag in AlGaN/GaN HEMTs. (© 2009 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Reduction of buffer‐related current collapse in GaN FETs under favour of a field plate

AbstractTwo‐dimensional transient analysis of GaN MESFETs with a semi‐insulating buffer layer is performed in which a deep donor and a deep acceptor are considered in the buffer layer, and the results are compared between the two cases with and without a field plate. It is shown that buffer‐related drain lag is reduced by introducing a field plate because trapping effects become smaller. It is also shown that current collapse and gate lag are also reduced in the field‐plate structure. The dependence on SiN passivation layer thickness is also studied, indicating that there is an optimum SiN thickness to minimize the buffer‐related current collapse and drain lag in GaN‐based FETs. (© 2008 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Analysis of buffer‐trapping effects on gate lag, drain lag and current collapse in AlGaN/GaN HEMTs

AbstractTransient simulations of AlGaN/GaN HEMTs are performed in which a deep donor and a deep acceptor are considered in a semi‐insulating buffer layer. Quasi‐pulsed I‐V curves are derived from the transient characteristics, and are compared with steady‐state I‐V curves. It is shown that the lag phenomena and current collapse could be reproduced. Particularly, the gate lag is correlated with relatively high source access resistance of the FETs. The current collapse is shown to bemore pronounced when the deep‐acceptor density in the buffer layer is higher and when an off‐state drain voltage is higher, because trapping effects become more significant. It is suggested that to minimize current collapse in AlGaN/GaN HEMTs, an acceptor density in the buffer layer should be made low, although the current cutoff behavior may be degraded. (© 2008 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Physical Mechanism of Buffer-Related Current Transients and Current Slump in AlGaN/GaN High Electron Mobility Transistors

Two-dimensional transient analyses of AlGaN/GaN high electron mobility transistors (HEMTs) are performed in which a deep donor and a deep acceptor are considered in a buffer layer. Quasi-pulsed current–voltage (I–V) curves are derived from the transient characteristics. When the drain voltage is raised abruptly, electrons are injected into the buffer layer and captured by deep donors, and when it is lowered abruptly, the drain currents remain at low values for some periods and begin to increase slowly as the deep donors begin to emit electrons, showing drain-lag behavior. The gate lag could also occur due to deep levels in the buffer layer, and it is correlated with relatively high source access resistance in AlGaN/GaN HEMTs. It is shown that the current slump is more pronounced when the deep-acceptor density in the buffer layer is higher and when an off-state drain voltage is higher, because the trapping effects become more significant. The drain lag could be a major cause of current slump in the case of higher off-state drain voltage. It is suggested that to minimize current slump in AlGaN/GaN HEMTs, an acceptor density in the buffer layer should be made low, although there may be a trade-off relationship between reducing current slump and obtaining sharp current cutoff.

Physically based model for trapping and self-heating effects in 4H-SiC MESFETs

In order to accurately and simply extract the trapping parameters in SiC metal semiconductor field effect transistors (MESFETs) a method is proposed based on device dc and ac small-signal models. By combining modeling techniques, material physics, and measured device characteristics, we are able to estimate the important information about the trap property and heat flow in 4H-SiC material and their influences on performance of MESFET devices, including gate lag, frequency-related dispersion, and the self-heating effect. Simulations indicate that the gate lag is due to the traps located at the channel/buffer interface and the transition frequency is up to ∼ MHz at 600 K.

Influence of pit defects on AlGaN surface and dislocation defects in GaN buffer layer on current collapse of AlGaN/GaN HEMTs

The influence of pit defects on AlGaN surface and dislocation defects in GaN buffer layer on the current collapse of MOVPE-grown AlGaN/GaN high electron mobility transistors (HEMTs) is studied in this paper. Pulsed gate voltage measurements show that the surface pit defects result in gate lag current collapse and increased of source/drain resistance. And the more pit defects exist, the more obvious current collapse and increased source/drain resistance are observed. Pulsed drain voltage measurements show that the drain lag current collapse, which is almost unaffected by the surface pit defects, can be associated with the dislocation defects in GaN buffer layer. Our experimental results indicate that pit defects on AlGaN surface and dislocation defects in GaN buffer layer can be one of the origins of gate lag and drain lag current collapse, respectively.

Analysis of buffer‐related lag phenomena and current collapse in GaN FETs

Drain-current responses of GaN MESFETs with a semi-insulating buffer layer are calculated when the drain voltage and/or the gate voltage are changed abruptly, and pulsed I-V curves are derived from them. It is shown that so-called current collapse or current slump is not so dependent on the gate length LG (0.3 μm – 1 μm), and this is essentially determined by a deep-acceptor density NDA in the buffer layer. LG and NDA dependence of gate lag is also studied, indicating that the gate lag is weaker for longer LG and the lag rate becomes high with NDA, although it may show a saturation behaviour. (© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Impacts of Gate Recess and Passivation on AlGaN/GaN High Electron Mobility Transistors

In this study, the impacts of gate recess and passivation on AlGaN/GaN high electron mobility transistors (HEMTs) were investigated. The trap-related characteristics were studied in detail by several different measurements including dc current–voltage, current collapse, gate lag, and flicker noise characterizations. With a Cl2/Ar-recessed gate, drain current collapse factors (ΔImax) of ∼37.5 and ∼6.9% were observed before and after SiN passivation. The gate lag measurements showed that the lagging phenomena almost disappear with SiN passivation for both Cl2- and Cl2/Ar-recessed devices. However, the flicker noise measurements revealed distinct noise levels of devices with different processes even after passivation. As the gate voltage (VG) changed from 2 to -4 V, the devices recessed by Cl2 exhibited lower drain noise current densities (SID/ID2 ranging from 2.8×10-14 to 1.7×10-12 Hz-1 at 1 kHz) than those etched by Cl2/Ar mixture gas (SID/ID2 ranging from 6.3×10-14 to 6.0×10-12 Hz-1 at 1 kHz), whereas the devices without the recess process showed the lowest noise levels (SID/ID2 ranging from 2.8×10-15 to 1.3×10-13 Hz-1 at 1 kHz). It was found that SID/ID2 increased monotonically when VG changed from 2 to -4 V. A bias dependence of the 1/ fγ slope γ was observed, and a relatively large variation in the range of ∼1.1 to 1.6 was found for devices recessed by Cl2/Ar mixture gas. The number fluctuation model was employed to explain the observed trends. The results also indicated that the surface traps play an important role in these devices.

Demonstration and dynamic analysis of trapping of hot electrons at gate edge model for current collapse and gate lag in GaN-based high-electron-mobility transistor including self-heating effect

Using a two-dimensional simulator, the authors report on demonstration of trapping of hot electrons at gate edge model in GaN-based high-electron-mobility transistors. Dynamic picture of hot electrons under gate pulse voltage is discussed in detail. Trapped charges may accumulate under punch-off gate voltage at gate edge drain side, where the electric field significantly changes and gate-voltage-dependent strain is induced. Significant band barrier is formed at the gate edges causing a notable current collapse. Self-heating effect is one of the reasons for current collapse and gate lag.

Simulation of slow current transients and current compression in AlGaAs/GaAs HFETs

Two-dimensional transient simulations of AlGaAs/GaAs HFETs are performed in which substrate traps and surface states are considered. When the drain voltage is raised abruptly, the drain current overshoots the steady-state value, and when it is lowered abruptly, the drain current remains at a low value, showing drain-lag behavior. Turn-on characteristics are also calculated when both the gate voltage and the drain voltage are changed abruptly, and quasi-pulsed I-V curves are derived from them. It is shown that the drain lag due to substrate traps could become a cause of so-called current compression of the HFETs. It is also shown that gate lag due to surface states could become a major cause of the current compression.

Study of the Impact of Electron Traps on GaN HEMT Reliability

In this paper, we will review work done at the Naval Research Laboratory that addresses GaN-based high electron mobility transistor (HEMT) reliability. Electron trapping effects are especially important in these wide bandgap devices, as they can limit microwave frequency performance and degrade reliability. We will review the utility of current collapse and gate lag measurements in characterizing nitride HEMT device performance. We will conclude with a discussion of the physical origin of these traps and work being done to reduce their density and mitigate their effects.

High Power-Density 4H-SiC RF MOSFETs

We have made a 4H-SiC RF power MOSFETs with cutoff frequency up to 12 GHz, delivering RF power of 1.9 W/mm at 3 GHz. The transistors withstand 200 V drain voltage, are normally-off, and show no gate lag, which is often encountered in SiC MESFETs. The measured devices have a single drain finger and a double gate finger and a total gate width of 0.8 mm. To our knowledge this is the first time that power densities above 1 W/mm at 3 GHz are reported for SiC MOSFETs.

High-power-density 4H-SiC RF MOSFETs

The authors have made the first 4H-SiC RF power MOSFETs with cutoff frequency up to 12 GHz, delivering RF power of 1.9 W/mm at 3 GHz. The transistors withstand 200 V drain voltage, are normally off, and show no gate lag, which is often encountered in SiC MESFETs. The measured devices have a single drain finger and a double gate finger, and a total gate width of 0.8 mm. To their knowledge, this is the first time that power densities above 1 W/mm at 3 GHz are reported for SiC MOSFETs.