Experimentally Validated Gate-Lag Simulations of AlGaN/GaN HEMTs Using Fermi Kinetics Transport

Abstract

This article presents for the first time a direct connection between gate lag observed in drain current transient measurements of gallium nitride (GaN) high-electron-mobility transistors (HEMTs) and traps located in the barrier of the transistor epitaxy. Semiclassical numerical simulations are presented using the Air Force Research Laboratory’s (AFRL’s) Fermi kinetics transport (FKT) solver and are validated with drain current transient measurements. Capacitance–voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C} - {V}$ </tex-math></inline-formula> ) and conductance–voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${G} - {V}$ </tex-math></inline-formula> ) measurements are also presented to provide further insights into the trap location used in the FKT simulations. These simulations indicate that equivalent defects located specifically at the AlGaN barrier/GaN cap interface of an AFRL GaN HEMT with a density of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.5\times 10^{{12}}$ </tex-math></inline-formula> cm−2 and positioned 1.464 eV below the GaN cap conduction band edge were the salient traps linked to the gate-lag phenomenon. The study highlights the importance of experimentally benchmarked device simulation for trapping analysis in GaN HEMTs and may provide significant insights into device engineers for mitigating trapping effects in state-of-the-art GaN technologies.