Gate Dielectric Thickness Research Articles

On the width of the recombination zone in ambipolar organic field effect transistors

The performance of organic light emitting field effect transistors is strongly influenced by the width of the recombination zone. We present an analytical model for the recombination profile. By assuming Langevin recombination, the recombination zone width W is found to be given byW=4.34dδ, with d and δ the gate dielectric and accumulation layer thicknesses, respectively. The model compares favorably to both numerical calculations and measured surface potential profiles of an actual ambipolar device.

Dielectric-thickness dependence of damage induced by electron-beam irradiation on metal nitride oxide semiconductor gate pattern

We analyzed the electron-irradiation damage induced by electron-beam inspection of metal nitride oxide semiconductor (MNOS) capacitors with various gate-dielectric thicknesses. Damage induced in an MNOS capacitor with a SiON dielectric for high-performance CMOS devices was compared to that induced on a metal oxide semiconductor (MOS) capacitor. We found that there is no remarkable difference between the damage to MOS capacitors and that to metal nitride oxide semiconductor MNOS capacitors. Damage was induced when a high-energy electron beam, whose electron range was larger than the thickness of the gate electrode, was irradiated. The induced damage strongly depends on the thickness of the gate dielectric. When the beam was irradiated onto a capacitor with a gate-dielectric thickness of 10.0 nm the flatband voltage shifted. When the beam was scanned onto a capacitor with a gate-dielectric thickness of 4.0 nm, the flatband voltage shifted minimally. However, the leakage-current density increased to 10−7 A/cm2 at a gate voltage of 3.0 V. On the other hand, when the beam was scanned onto an MNOS capacitor with 2.5-nm-thick dielectric, not even the leakage current was increased. Accordingly, for damage-free inspection when a gate-dielectric thickness is 4.0 nm or more, the beam energy needs to be lower so that the electron range is shorter than the thickness of the gate electrode.

Enhanced Subthreshold Slopes in Large Diameter Single Wall Carbon Nanotube Field Effect Transistors

The performance of single wall carbon nanotube field effect transistors (SWNT FETs) is greatly affected by the quality of its contacts. The presence of Schottky barriers imposes a strong scaling of the gate dielectric thickness. Here, we employ large diameter SWNTs in order to fabricate ohmically contacted FETs when a lower work function but higher adhesion strength metal such as Cr is used. A subthreshold slope as low as 113 mV/dec is obtained even when employing a thick, 200 nm SiO2 dielectric. The result is examined in light of the positive effects of exposure to air and underlines the possibility for less stringent device fabrication techniques.

Performance and transport characteristics of α,ω-dihexylsexithiophene- based transistors with a high room-temperature mobility of 0.16cm2∕Vs

Organic thin-film transistors (OTFTs) based upon α,ω-dihexylsexithiophene (DH6T) have been fabricated and characterized. The DH6T thin films were prepared using neutral cluster beam deposition (NCBD) methods on room-temperature SiO2 substrates. The effects of surface modification were examined. The geometric effects of the gate dielectric thickness, channel length, and width on the device characteristics were also systematically studied. A combination of the NCBD technique and octadecyltrichlorosilane (OTS) pretreatment was most efficient for producing high-quality crystalline DH6T films. The temperature dependence of the field-effect mobility (μeff) indicated that the transistor performance was strongly correlated with the structural and morphological properties of the DH6T active layers and that the surfactant pretreatment significantly enhanced the μeff. A room-temperature μeff of 0.16cm2∕Vs for the OTS-pretreated transistors was found to be best so far reported for DH6T-based OTFTs using a SiO2 gate dielectric layer.

Advanced Metal Gate FinFET CMOS TEchnology

We have developed the advanced metal gate technologies for materializing FinFET CMOS circuits. Using the developed titanium nitride (TiN) gate technologies, we demonstrate the fin-height controlled FinFET CMOS with accurate current matching and the flexible threshold voltage (Vth) asymmetric gate insulator thickness four-terminal (4T) FinFETs with a greatly improved subthreshold slope (S-slope). Furthermore, the newly developed nitrogen gas flow ratio, RN = N2/(Ar + N2), controlled PVD TiN gate and the tantalum (Ta)/molybdenum (Mo) interdiffusion gate technologies to set the symmetrical and lower Vth's for FinFET CMOS are presented.

High-κ dielectrics and advanced channel concepts for Si MOSFET

With scaling of the gate length downward to increase speed and density, the gate dielectric thickness must also be reduced. However, this practice which has been in effect for many decades has reached a fundamental limitation because gate dielectric thicknesses in the range of tunneling have been reached with the SiO2 dielectric layer for MOSFETs. Consequently, the gate dielectrics with higher dielectric constants, dubbed the “high-κ”, which allow scaling with much larger thicknesses have become active research and development topics. In this review technological issues associated with the likely high-κ materials which are under consideration as well as challenges, and solution to them, they bring about in the fabrication of Si MOSFET are discussed. Moreover, in order to squeeze more speed out of CMOS, channels for both n- and p-type MOSFET enhanced with appropriate strain and the concepts behind them are discussed succinctly. Finally, the longer term approach of replacing Si with other channel materials such as GaAs (InGaAs) for n-channel and Ge for p-channel along with technological developments of their preparation on Si and likely gate oxide developments are treated in some detail.

Analysis of the Effects of Fringing Electric Field on FinFET Device Performance and Structural Optimization Using 3-D Simulation

In this paper, the potential impact of parasitic capacitance resulting from fringing field on FinFET device performance is studied in detail using a 3-D simulator implemented with quantum-mechanical models. It was found that fringing field from gate to source contributes significantly to FinFET performance and speed. The strength of fringing field is closely related to device features such as gate-dielectric thickness, the spacer width, fin width and pitch, as well as the gate height. For undoped fin with underlapping (nonoverlapping source/drain) gate, a thinner spacer with higher kappa value enhances the gate control of short-channel effects (SCEs) and reduces the source-to-drain leakage current. Our results also suggest that reducing the high- gate-dielectric thickness is no longer an effective approach to improve performance in small FinFET devices due to the strong fringing effect. However, the introduction of thin metal gate in a multifin device was found beneficial to device speed without compromising on current drive and SCE.

Compact model for short channel symmetric doped double-gate MOSFETs

A new compact model for currents in short channel symmetric double-gate MOSFETs is presented which considers a doped silicon layer in the range of concentrations between 1014 and 3×1018cm−3. The mobile charge density is calculated using analytical expressions obtained from modeling the surface potential and the difference of potentials at the surface and at the center of the Si doped layer without the need to solve any transcendental equations. Analytical expressions for the current–voltage characteristics are presented, as function of silicon layer impurity concentration, gate dielectric and silicon layer thickness, including variable mobility. The short channel effects included are velocity saturation, DIBL, VT roll-off, channel length shortening and series resistance. Comparison of modeled with simulated characteristics obtained in ATLAS device simulator for the transfer characteristics in linear and saturation regions, as well for as output characteristics, show good agreement within the practical range of gate and drain voltages, as well as gate dielectric and silicon layer thicknesses. The model can be easily introduced in circuit simulators.

Electrical transport of bottom-up grown single-crystalSi1−xGex nanowire

In this work, we fabricated an Si1−xGex nanowire (NW) metal-oxide-semiconductor field-effecttransistor (MOSFET) by using bottom-up grown single-crystalSi1−xGex NWsintegrated with HfO2 gate dielectric, TaN/Ta gate electrode and Pd Schottky source/drainelectrodes, and investigated the electrical transport properties ofSi1−xGex NWs. It is found that both undoped and phosphorus-dopedSi1−xGex NW MOSFETs exhibit p-MOS operation while enhanced performance of higherIon∼100 nA andIon/Ioff∼105 are achieved fromphosphorus-doped Si1−xGex NWs, which can be attributed to the reduction of the effective Schottky barrierheight (SBH). Further improvement in gate control with a subthreshold slope of142 mV dec−1 was obtainedby reducing HfO2 gate dielectric thickness. A comprehensive study on SBH between theSi1−xGex NW channel and Pd source/drain shows that a dopedSi1−xGex NW has a lower effective SBH due to a thinner depletion width at the junction and thegate oxide thickness has negligible effect on effective SBH.

Influence of Si/SiO 2 interface properties on electrical performance and breakdown characteristics of ultrathin stacked oxide/nitride dielectric films

In this work, the influence of Si/SiO 2 interface properties, interface nitridation and remote-plasma-assisted oxidation (RPAO) thickness (<1 nm), on electrical performance and TDDB characteristics of sub-2 nm stacked oxide/nitride gate dielectrics has been investigated using a constant voltage stress (CVS). It is demonstrated that interfacial plasma nitridation improves the breakdown and electrical characteristics. In the case of PMOSFETs stressed in accumulation, interface nitridation suppresses the hole traps at the Si/SiO 2 interface evidenced by less negative V t shifts. Interface nitridation also retards hole tunneling between the gate and drain, resulting in reduced off-state drain leakage. In addition, the RPAO thickness of stacked gate dielectrics shows a profound effect in device performance and TDDB reliability. Also, it is demonstrated that TDDB characteristics are improved for both PMOS and NMOS devices with the 0.6 nm-RPAO layer using Weibull analysis. The maximum operating voltage is projected to be improved by 0.3 V difference for a 10-year lifetime. However, physical breakdown mechanism and effective defect radius during stress appear to be independent of RPAO thickness from the observation of the Weibull slopes. A correlation between trap generation and dielectric thickness changes based on the C– V distortion and oxide thinning model is presented to clarify the trapping behavior in the RPAO and bulk nitride layer during CVS stress.

Cutoff frequency characteristics of gate‐controlled hot‐electron transistors by Monte Carlo simulation

AbstractThe high‐speed characteristics and off characteristics of a novel transistor with a hot‐electron launcher and a transit layer of an intrinsic semiconductor whose current is controlled by an insulated gate are evaluated by Monte Carlo simulation. The dependences of the cutoff frequency fT on the gate insulator thickness, collector bias voltage, gate length and transit layer length are clarified. For the optimum structure consisting of InP/InGaAs/W as the emitter/transit layer/collector, Au as the gate and bisbenzocyclobutene (BCB) as the gate insulator and the surrounding material, fT is 1.4 THz at the collector current density of 1.6 MA/cm2. The collector current can be controlled over four orders of magnitude by a gate voltage swing of 0.6 V. (© 2008 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Thickness Dependence of Gate Dielectric and Active Semiconductor on InGaZnO[sub 4] TFT Fabricated on Plastic Substrates

We investigated the thickness dependence of a room-temperature grown MgO 0.3 BST 0.7 composite gate dielectric and an InGaZnO 4 active semiconductor on the electrical characteristics of thin-film transistors (TFTs) fabricated on a polyethylene terephthalate substrate. The optimum gate dielectric and active semiconductor thickness were 300 and 30 nm, respectively. The TFT showed a high field-effect mobility of 21.34 cm 2 /V s, an on/off ratio of 8.27 X 10 6 , a threshold voltage of 2.2 V, and a subthreshold swing of 0.42 V/dec.

Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETs

Analytical expressions are presented to model the behavior of the potential at the surface and the difference of potentials at the surface and at the center of the doped silicon layer as function of silicon layer impurity concentration, gate dielectric thickness, silicon layer thickness and applied voltages in double-gate MOSFETs that considers for the first time a doped silicon layer in a range of concentrations between 10 14 and 3 × 10 18 cm −3. No fitting parameters are required. All the equations obtained for the potentials were validated using a rigorous numerical calculation for different doping concentrations, as well as for several double-gate structure dimensions and applied voltages. Calculation of the threshold voltage using the derived expressions was also validated with ATLAS simulations. The expressions presented in the paper can be used directly for modeling current and capacitance in doped double-gate MOSFET.

Modeling of electron mobility in gated silicon nanowires at room temperature: Surface roughness scattering, dielectric screening, and band nonparabolicity

We present a theoretical study of electron mobility in cylindrical gated silicon nanowires at 300 K based on the Kubo-Greenwood formula and the self-consistent solution of the Schrödinger and Poisson equations. A rigorous surface roughness scattering model is derived, which takes into account the roughness-induced fluctuation of the subband wave function, of the electron charge, and of the interface polarization charge. Dielectric screening of the scattering potential is modeled within the random phase approximation, wherein a generalized dielectric function for a multi-subband quasi-one-dimensional electron gas system is derived accounting for the presence of the gate electrode and the mismatch of the dielectric constant between the semiconductor and gate insulator. A nonparabolic correction method is also presented, which is applied to the calculation of the density of states, the matrix element of the scattering potential, and the generalized Lindhard function. The Coulomb scattering due to the fixed interface charge and the intra- and intervalley phonon scattering are included in the mobility calculation in addition to the surface roughness scattering. Using these models, we study the low-field electron mobility and its dependence on the silicon body diameter, effective field, dielectric constant, and gate insulator thickness.

Improved Compact Model for Symmetric Doped Double-Gate MOSFETs

This paper complements our new compact analytical model for long and short channel symmetric double-gate MOSFETs, which for the first time, considered a doped silicon layer in a wide range of concentrations, between 1014 and 3x1018 cm-3. The already incorporated short channel effects that included threshold voltage variation, DIBL, channel shortening and saturation velocity were further revised and the series resistance effect was included. The model uses the charge control procedure, where the mobile charge density is modeled as function of silicon layer impurity concentration; gate dielectric and silicon layer thickness and applied voltages. Comparison of modeled and simulated (using the ATLAS device simulator) transfer characteristics in linear and saturation regions, as well as output characteristics, shows a good agreement within the practical range of gate and drain voltages and silicon layer doping concentrations.

High Transconductance MISFET With a Single InAs Nanowire Channel

Metal-insulator field-effect transistors (FETs) are fabricated using a single n-InAs nanowire (NW) with a diameter of d = 50 nm as a channel and a silicon nitride gate dielectric. The gate length and dielectric scaling behavior is experimentally studied by means of dc output- and transfer-characteristics and is modeled using the long-channel MOSFET equations. The device properties are studied for an insulating layer thickness of 20-90 nm, while the gate length is varied from 1 to 5 mum. The InAs NW FETs exhibit an excellent saturation behavior and best breakdown voltage values of V BR > 3 V. The channel current divided by diameter d of an NW reaches 3 A/mm. A maximum normalized transconductance gm /d > 2 S/mm at room temperature is routinely measured for devices with a gate length of les 2 mum and a gate dielectric layer thickness of les 30 nm.

Physical Understanding of Gate-Depletion Phenomena in Poly-Si/HfSiON Stacks Based on $C$–$V$ Differentiation Analysis

We propose sub-1-A-resolution analysis of gate surface layer In scaled-Tinv (capacitance equivalent thickness at substrate inversion) gate stacks by differentiating their C-V curves. By introducing the universal derivative-of-capacitance curve, gate stacks with different equivalent oxide thickness of gate insulator and substrate-impurity concentration JVSub can be analyzed in one and the same plot. By applying this analysis technique to p+ poly-Si/HfSiON stack, it is found that gate depletion increases due to both lower poly impurity concentration Npoly and high pinning charge density Nox inside the dielectric. Ultrathin SiN cap insertion onto HfSiON recovers the degradation in Npoly and Nox leading to suppression of gate depletion and flatband voltage shift.

Accurate Gate Impedance Determination on Ultraleaky MOSFETs by Fitting to a Three-Lumped-Parameter Model atFrequencies From DC to RF

We present an experimental methodology that demonstrates the suitability of the conventional three-lumped- parameter model for gate impedance of MOSFET devices at frequencies from dc to the gigahertz range, which permits accurate extraction of model parameters. The parasitic effects at a high frequency are minimized by using radio frequency techniques (i.e., short return paths and de-embedding structures), whereas a robust parameter extraction algorithm overcomes possible instrument inaccuracies. When combined, these allow simultaneous extraction of all three parameters (i.e., Cgate, RDT and Rseries) from the model. The technique is applied to conventional SiO2 -based MOSFET devices and to ultraleaky HfO2 devices with aggressively scaled gate dielectric thickness.

Room temperature deposited indium zinc oxide thin film transistors

Depletion-mode indium zinc oxide (IZO) channel thin film transistors were fabricated on glass substrates from layers deposited at room temperature using rf magnetron sputtering. The threshold voltage was in the range from −5.5to−6.5V depending on gate dielectric (SiO2) thickness and the drain current on-to-off ratio was ∼105. The maximum field effect mobility in the channel was ∼4.5cm2V−1s−1, lower than the Hall mobility of ∼17cm2V−1s−1 in the same layers, suggesting a strong influence of scattering due to trapped charges at the SiO2-IZO interface. The low deposition and processing temperatures make these devices suitable for applications requiring flexible substrates.

Thermal annealing effect on electrical properties of metal nitride gate electrodes with hafnium oxide gate dielectrics in nano-metric MOS devices

Electrical properties of hafnium oxide (HfO 2) gate dielectric with various metal nitride gate electrodes, i.e., tantalum nitride (TaN), molybdenum nitride (MoN), and tungsten nitride (WN), were studied over a range of HfO 2 thicknesses, e.g., 2.5–10 nm, and post-metal annealing (PMA) temperatures, e.g., 600 °C to 800 °C. The work function of the nitride gate electrode was dependent on the material and the post-metal annealing (PMA) temperature. The scanning transmission electron microscopy technique is used to observe the effect of PMA on the interfacial gate dielectric thickness. After high-temperature annealing, the metal nitride gates were suitable for NMOS. At the same PMA temperature, the oxide-trapped charges increased and the interface state densities decreased with the increase of the HfO 2 thickness for TaN and WN gate electrodes. However, for MoN gate electrode the interface state density is almost independent of film thickness. Therefore, dielectric properties of the HfO 2 high- k film depend not only on the metal nitride gate electrode material but also the post-metal annealing condition as well as the film thickness. During constant voltage stress of the MOS capacitors, an increase in the time-dependent gate leakage current is also observed.