Gate Dielectric Thickness Research Articles

Low voltage operation in picene thin film field-effect transistor and its physical characteristics

Low voltage operation of picene thin film field-effect transistor (FET) has been realized with 40 nm thick SiO2 gate dielectrics coated by two polymers, Cytop™ and polystyrene. The picene FETs operated in low absolute gate voltage |VG| below 15 V for Cytop™ coated SiO2 and 30 V for polystyrene coated SiO2 gate dielectrics, and they showed a significant O2 gas sensing effect down to ∼10 ppm. Photoemission spectrum clarified that O2 molecules penetrate into the thin films at O2/picene mole ratio of 1: 1. X-ray diffraction pattern of picene thin films showed highly oriented growth on the polymer-coated SiO2.

DC gain analysis of scaled CMOS op amp in Sub-100 nm technology nodes: A research based on channel length modulation effect

Metal-oxide-semiconductor field effect transistor (MOSFET) intrinsic gain degradation caused by channel length modulation (CLM) effect is examined. A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4 (BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced, which only needs a few technology parameters. With this transistor intrinsic gain model, complementary metal-oxide-semiconductor (CMOS) operational amplifier (op amp) DC gain could be predicted. A two-stage folded cascode op amp is used as an example in this work. Non-minimum length device is used to improve the op amp DC gain. An improvement of 20 dB is proved when using doubled channel length design. Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain. After these, a full op amp DC gain scaling roadmap is proposed, from 130 nm technology node to 32 nm technology node. Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB. Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology. The prediction based on our simplified gain model agrees with SPICE simulation results.

InAs-Channel Metal-Oxide-Semiconductor HEMTs with Atomic-Layer-Deposited Al2O3 Gate Dielectric

The performance of n-type metal-oxide-semiconductor HEMTs with an InAs-channel using atomic-layer-deposited Al2O3 as gate dielectric has been fabricated and evaluated. The device performances of a set of scaled transistors with different gate dielectric thicknesses of 3, 5 and 7 nm have been investigated to determine whether the architecture of Al2O3 dielectric on InAs-channel HEMT can demonstrate good properties at low bias conditions for high-speed, high performance CMOS applications. The results indicate that the high-performance InAs-channel MOS-HEMTs with an ALD Al2O3 gate dielectric are promising candidates for advanced post-Si CMOS applications.

A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs

A new 3-D gate capacitor model is developed to accurately calculate the parasitic capacitances of nanoscale CMOS devices. The dependences on gate length and width, gate electrode and dielectric thicknesses, gate-to-contact spacing, and contact dimension and geometry are fully incorporated in this model. The accuracy is certified by an excellent match with the 3-D interconnection simulation results for three structures with strip, square, and circular contacts. The features of being free from fitting parameters and proven accuracy over various geometries make this model useful for nanoscale MOSFET parasitic capacitance simulation and analysis. Furthermore, the developed capacitor model in the form of multidimensional integral can easily be deployed in general circuit simulators. This model predicts that the parasitic capacitance <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">of</sub> dominates around 25% of the intrinsic gate capacitance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gint</sub> ) in 80-nm MOSFETs and that the near nonscalability with gate length brings the weighting factor <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">of</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gint</sub> above 30%/40%/60% in 65-/45-/32-nm devices. It actually exceeds the limitation defined by the most updated ITRS and reveals itself as a show-stopper in high-speed and high-frequency circuit design.

Performance Analysis of 60-nm Gate-Length III–V InGaAs HEMTs: Simulations Versus Experiments

An analysis of recent experimental data for high-performance In0.7Ga0.3As high electron mobility transistors (HEMTs) is presented. Using a fully quantum mechanical, ballistic model, we simulate In0.7Ga0.3As HEMTs with gate lengths of LG = 60nm, 85, and 135 nm and compare the result to the measured I-V characteristics including draininduced barrier lowering, sub-threshold swing, and threshold voltage variation with gate insulator thickness, as well as on-current performance. To first order, devices with three different oxide thicknesses and channel lengths can all be described by our ballistic model with appropriate values of parasitic series resistance. For high gate voltages, however, the ballistic simulations consistently overestimate the measured on-current, and they do not show the experimentally observed decrease in on-current with increasing gate length. With no parasitic series resistance at all, the simulated on-current of the LG = 60 nm device is about twice the measured current. According to the simulation, the estimated ballistic carrier injection velocity for this device is about 2.7 x 10^7 cm/s. Because of the importance of the semiconductor capacitance, the simulated gate capacitance is about 2.5 times less than the insulator capacitance. Possible causes of the transconductance degradation observed under high gate voltages in these devices are also explored. In addition to a possible gate-voltage dependent scattering mechanism, the limited ability of the source to supply carriers to the channel, and the effect of nonparabolicity are likely to play a role. The drop in on-current with increasing gate length is an indication that the devices operate below the ballistic limit.

Effect of the hydrophobicity and thickness of polymer gate dielectrics on the hysteresis behavior of pentacene-based field-effect transistors

We demonstrate the origin and mechanism of the hysteresis behavior that is frequently observed during the operation of organic field-effect transistors (OFETs) based on polymer gate dielectrics. Although polar functionalities, such as hydroxyl groups, present in the polymer gate dielectrics are known to induce hysteresis, there have only been a few detailed investigations examining how the presence of such end functionalities both at the polymer surface—forming an interface with the semiconductor layer—and in the bulk influences the hysteresis. In this study, we control the hydrophobicity of the polymer by varying the number of hydroxyl groups, and use an ultrathin polymer/SiO2 bilayer and a thick single polymer as the gate dielectric structure so that the hysteresis behavior is divided into contributions from hydroxyl groups present at the polymer surface and in the bulk, respectively. Electrical characterizations of the OFETs, performed both in vacuum (≈10−3 Torr) and in ambient air (relative humidity of about 40%), show that the observed hysteresis is determined by the transport of water within the polymer (i.e., the adsorption at the polymer surface and the diffusion into the bulk), which in turn is controlled by the hydrophobicity and the thickness of the polymer.

A continuous surface-potential solution from accumulation to inversion for intrinsic symmetric double-gate MOSFETs

A continuous surface-potential solution of Poisson's equation is derived for intrinsic (or lightly doped) symmetric double-gate (DG) Metal-Oxide-Semiconductor-Field-Effect-Transistors (MOSFETs). The resulting expression is smooth and continuous from accumulation through depletion to inversion regions. The dependences of the surface potential on various physical parameters including the quasi-Fermi potential, silicon film thickness, gate dielectric thickness and temperature are studied and compared with 2-D numerical simulation. Excellent agreements between them suggest that the proposed surface-potential solution is accurate over a wide range of physical parameters and can be used in surface-potential-based symmetric DG MOSFET modelling.

Novel tapered macrogate structure for carbon nanotube based field emission display

The tapered macrogate (TMG) structure is proposed to overcome the difficulties in carbon nanotube (CNT) based field emission display (FED) with high-voltage phosphors used in cathode ray tube screens. In order to achieve an ideal triode operation for field emission devices, the TMG was designed to have a very thick gate insulator with the inclined gate holes compared with the CNT emitters. The inclined gate holes with a narrower outlet than the bottom of the hole were shown to protect the CNT emitters from the anode field perfectly, enabling the authors to apply a high anode voltage over 10 kV needed for high-voltage FED. Also, the TMG structure had additional useful functions such as an electron-beam self-focusing and high durability against electrical damage. The authors successfully fabricated and demonstrated a 5 in. active-matrix CNT-FED panel with the TMG, showing color moving images with a low addressing voltage of about 15 V using amorphous silicon thin-film transistor as a switching device.

Extended Scalability of HfON/SiON Gate Stack Down to 0.57 nm Equivalent Oxide Thickness with High Carrier Mobility by Post-Deposition Annealing

We discuss scaling the equivalent oxide thickness (EOT) of Hf-based high-k gate dielectrics by post-deposition annealing (PDA). Thin HfON/SiON gate stacks with EOT=0.57 nm were successfully formed by repeating ultra thin (0.6 nm) HfO2 deposition and high-temperature (950 °C) PDA on a previously formed SiON interfacial layer. Physical and electrical analyses revealed that the reduction in EOT was due to crystallization of HfON to the tetragonal phase which has a higher dielectric constant than the amorphous and other crystalline phases. It was also found that Hf diffusion in the SiON interfacial layer was induced by the high-temperature PDA treatment. This also improved the k-value of the interfacial layer and enabled aggressive scaling even when using a SiO2-based interfacial layer. The electron mobility of the gate stack is higher than those in the previous reports, indicating that a high quality interface is realized using this approach. The reduction in EOT together with the excellent interfacial quality demonstrated in the present study shows that this technique is a promising solution for the 22-nm-node and beyond.

Thermal stability of HfTaON films prepared by physical vapor deposition

We investigate the thermal stability of HfTaON films prepared by physical vapor deposition using high resolution transmission electronic microscope (HRTEM) and X-ray photoelectron spectroscopy (XPS). The results indicate that the magnetron-sputtered HfTaON films on Si substrate are not stable during the post-deposition annealing (PDA). HfTaON will react with Si and form the interfacial layer at the interface between HfTaON and Si substrate. Hf–N bonds are not stale at high temperature and easily replaced by oxygen, resulting in significant loss of nitrogen from the bulk film. SiO2 buffer layer introduction at the interface of HfTaON and Si substrate may effectively suppress their reaction and control the formation of thicker interfacial layer. But SiO2 is a low k gate dielectric and too thicker SiO2 buffer layer will increase the gate dielectric's equivalent oxide thickness. SiON prepared by oxidation of N-implanted Si substrate has thinner physical thickness than SiO2 and is helpful to reduce the gate dielectric's equivalent oxide thickness.

Light-sensing circuits fabricated using new phototransistors

Since the demonstration of the first organic field-effect transistor (OFET) in the early 1980s,1 organic semiconductors have been seen as an alternative to conventional inorganic microelectronics for various low-end applications. Properties such as solution processability allow organic semiconductor devices to be fabricated at low temperatures using high-throughput fabrication methods. This makes the realization of certain organic devices potentially easier and cheaper than their inorganic counterparts. The field of OFETs has been growing rapidly. Bifunctional ambipolar light-sensing OFETs, or phototransistors,2 are a new addition to the family of organic devices, and could one day lead to the production of novel, low-cost image sensors. Unfortunately, all organic phototransistors demonstrated to date operate at relatively high voltages (>20V). This characteristic renders the technology unsuitable for portable, low-power applications. For widespread commercial use of the technology, devices with low-voltage and low-power dissipation would need to be developed. The operating voltage of organic transistors depends on the thickness and type of gate insulator used. The application of selfassembled monolayer (SAM) molecules as gate dielectrics has proven effective in reducing the gate dielectric’s thickness while retaining good insulating properties.3, 4 By combining such SAM dielectrics with hole/electron (pand n-type semiconductors) transporting organic heterojunctions, we havemade organic ambipolar phototransistors with operating voltages below 3V. A unique advantage of our approach is that hole and electron transport can be individually controlled and optimized. The spectral response of these ambipolar phototransistors can also be tuned through the use of suitable semiconductor systems. The schematic diagram of a bilayer (pentacene/[6,6]-phenylC61-butyric acid methyl ester or [60]PCBM) ambipolar lowvoltage organic phototransistor is shown in the inset of Figure 1. Under illumination (λmax= 469nm), the current flowing across Figure 1. Transfer characteristics from a low-voltage ambipolar organic phototransistor measured in the dark and under illumination using a blue (469nm) LED at different intensities in mW/cm2. Inset shows a schematic of the bilayer (pentacene/[6,6]-phenyl-C61-butyric acid methyl ester or [60]PCBM) transistor structure that was used. ID: Illumination of the current flowing between the source-drain electrodes in the ambipolar (A) phototransistor. VD: Drain voltage in volts. VG: Gate voltage.

Dielectric scaling of a top gate silicon nanowire on insulator transistor

The effects of gate dielectric constant and thickness on the performance of a top gate silicon nanowire on insulator transistor are studied using three-dimensional quantum simulation. The replacement of SiO2 by a high-K dielectric improves the off-state current, the on/off-current ratio, the inverse subthreshold slope, and the channel transconductance and degrades the switching performance. The high-K gate dielectric provides better control of the channel potential, especially in the off-state, and improves the off-state tunneling current by almost two orders of magnitude. With high-K dielectric, the switching performance degrades primarily due to increase in gate capacitance. The gate has better control of channel potential with thinner oxide. The on/off-current ratio, inverse subthreshold slope, channel transconductance, and the switching performance improve with thinner gate oxide. Our device of 10 nm gate length, 1 nm oxide with dielectric constant of 10, has an on/off-current ratio of 1.16×108, an inverse subthreshold slope of 70.5 mV/decade, and the intrinsic unity current gain frequency of 2.7414 THz.

Accurate Intrinsic Gate Capacitance Model for Carbon Nanotube-Array Based FETs Considering Screening Effect

In this letter, an accurate semi-analytical model for the intrinsic gate capacitance of carbon nanotube (CN)-array based back-gated field-effect transistors (FETs) is proposed. The model accounts for electrostatic screening effect for any given number of nanotubes, their diameter, pitch, and gate-dielectric thickness. It is shown that screening effect varies significantly not only with the change in density but also with the number of nanotubes and must be considered while modeling the intrinsic gate capacitance of array-based CNFETs for both high-performance and thin-film transistor applications.

Gallium oxide and gadolinium gallium oxide insulators on Si δ-doped GaAs/AlGaAs heterostructures

Test devices have been fabricated on two specially grown GaAs/AlGaAs wafers with 10 nm thick gate dielectrics composed of either Ga2O3 or a stack of Ga2O3 and Gd0.25Ga0.15O0.6. The wafers have two GaAs transport channels either side of an AlGaAs barrier containing a Si δ-doping layer. Temperature dependent capacitance-voltage (C-V) and current-voltage (I-V) studies have been performed at temperatures between 10 and 300 K. Bias cooling experiments reveal the presence of DX centers in both wafers. Both wafers show a forward bias gate leakage that is by a single activated channel at higher temperatures and by tunneling at lower temperatures. When Gd0.25Ga0.15O0.6 is included in a stack with 1 nm of Ga2O3 at the interface, the gate leakage is greatly reduced due to the larger band gap of the Gd0.25Ga0.15O0.6 layer. The different band gaps of the two oxides result in a difference in the gate voltage at the onset of leakage of ∼3 V. However, the inclusion of Gd0.25Ga0.15O0.6 in the gate insulator introduces many oxide states (≥4.70×1012 cm−2). Transmission electron microscope images of the interface region show that the growth of a Gd0.25Ga0.15O0.6 layer on Ga2O3 disturbs the well ordered Ga2O3/GaAs interface. We therefore conclude that while including Gd0.25Ga0.15O0.6 in a dielectric stack with Ga2O3 is necessary for use in device applications, the inclusion of Gd decreases the quality of the Ga2O3/GaAs interface and near interface region by introducing roughness and a large number of defect states.

Sub-9 Å equivalent oxide thickness scaling using hafnium zirconate dielectric with tantalum carbide gate

This paper reports on hafnium zirconate (HfxZr1−xO2) gate dielectric capacitance equivalent thickness scaling below 14 Å and equivalent oxide thickness scaling below 9 Å. This is accomplished by careful optimization of the HfxZr1−xO2 thickness and ammonia (NH3) postdeposition anneal (PDA) conditions with tantalum carbide (TaxCy) metal gate. Further, the various process schemes employed for the thickness scaling such as pretreatment, PDA, metal capping, and metal-oxide doping of HfxZr1−xO2 will be described. Finally, the attributes and possible mechanisms of NH3 PDA to reduce the thickness of interfacial layer and the thickness of the HfxZr1−xO2 layer for the oxide thickness scaling will be discussed.

Improved sensing characteristics of MISiC Schottky-diode hydrogen sensor by using HfO 2 as gate insulator

Hafnium dioxide deposited by RF sputtering is used as the gate insulator of metal–insulator–silicon–carbide (MISiC) Schottky-diode hydrogen sensors. Sensors with different gate insulator thicknesses are fabricated for investigation. Their hydrogen-sensing properties are compared with each other by taking measurements at various temperatures and hydrogen concentrations using a computer-controlled measurement system. Experimental results show that for the same insulator thickness, the HfO 2 sensor is more sensitive than its SiO 2 counterpart. This should be mainly attributed to the larger barrier-height at the Pt/HfO 2 interface which can reduce the current of the sensor before hydrogen exposure. Moreover, the sensitivity initially increases with the thickness of the HfO 2 film because a thicker oxide layer can provide a larger barrier-height reduction upon hydrogen exposure. However, further increasing the thickness of the HfO 2 dielectric beyond about 3.3 nm reduces the sensitivity, possibly due to more trapped charges in thicker high- k dielectric which can screen the effect of the polarized hydrogen layer.

Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Forward body biasing is a promising approach for realizing optimum threshold-voltage <formula formulatype="inline"><tex Notation="TeX">$(V_{\rm TH})$</tex></formula> scaling in the era when gate dielectric thickness can no longer be scaled down. This is confirmed experimentally and by simulation of a 10-nm gate length MOSFET. Because forward body bias <formula formulatype="inline"><tex Notation="TeX">$(V_{F})$</tex></formula> decreases the depletion width <formula formulatype="inline"><tex Notation="TeX">$(X_{\rm DEP})$</tex></formula> in the channel region, it reduces <formula formulatype="inline"><tex Notation="TeX">$V_{\rm TH}$</tex></formula> rolloff significantly. MOSFET performance is maximized under forward body bias with steep retrograde channel doping, and such channel doping profiles are required to accomplish good short-channel behavior (small <formula formulatype="inline"><tex Notation="TeX">$X_{\rm DEP}$</tex> </formula>) at low <formula formulatype="inline"><tex Notation="TeX">$V_{\rm TH}$</tex></formula> notwithstanding body bias; therefore, the combination of forward body biasing with steep retrograde channel doping profile can extend the scaling limit of conventional bulk-Si CMOS technology to 10-nm gate length MOSFET. Considering forward biased p-n junction current, parasitic bipolar transistor, and CMOS latch-up phenomena, the upper limit for <formula formulatype="inline"><tex Notation="TeX">$\vert V_{F}\vert$</tex></formula> should be set at 0.6–0.7 V, which is sufficient to realize significant advantages of forward body biasing. </para>

Gate dielectric scaling of top gate carbon nanoribbon on insulator transistors

The effects of gate dielectric constant and thickness on the performance of top gate carbon nanoribbon on insulator transistors are studied using a π-orbital quantum simulation model. The focus is on both the zero Schottky barrier (SB) source-drain contacts and the metal-oxide-semiconductor field effect transistor (MOSFET)-like doped source-drain contacts. The gate dielectric constant has little effect on the on/off current ratio, channel transconductance gm, and switching performance in SB contact devices. However, the on/off current ratio, the channel transconductance, and the switching performance significantly improve with high-K gate dielectric in doped contact devices. The physics is related to the modulation of the tunnel barrier. In SB contact devices, the on-state current is limited by the SB, and therefore, the improvement in on/off current ratio and transconductance is insignificant. However, the tunnel barrier modulation in the subthreshold regime is similar in both types of contact and the inverse subthreshold slope has similar improvement with high-K gate dielectrics. The unity current gain frequency (fT=gm/2πCg) degrades with high-K gate dielectric in SB contact devices and improves in doped contact devices. This is because the gate capacitance does not change much with dielectric constant and gm has a significant improvement in doped contact devices. The device performance improves with thinner gate oxide. The on/off current ratio and the inverse subthreshold slope scale as square root of oxide thickness.

Tunneling Effective Mass of Electrons in Lightly N-Doped $\hbox{SiO}_{x} \hbox{N}_{y}$ Gate Insulators

In this paper, we study the dependence of the tunneling effective mass of electrons on gate dielectric nitrogen concentration and thickness in MOSFETs with lightly doped silicon oxynitride (SiOxNy) gates. The direct tunneling current is modeled by applying a Schrodinger-Poisson solver with one-side-open boundary condition. The dependences of the effective mass on nitrogen concentration and dielectric thickness are extracted by fitting the computation results for the gate leakage current to the experimental data that we measured for samples with different thicknesses and nitrogen concentrations. Nitrogen concentration and thickness of samples are determined using X-ray photoemission spectroscopy. The obtained results show a strong dependence of the effective mass on the sample thicknesses and nitrogen concentration. The electron effective mass is found to increase as the thickness decreases, and the higher nitrogen concentration causes a reduction in effective mass.

Nano Gate Dielectrics for Low Voltage Operation of Organic Thin Film Transistors

Two types of nanometer thick gate dielectrics were employed in order to implement a low voltage operation for organic thin film transistors (OTFT). The first device used an organic monolayer that was formed through a self-assembly process of (benzyloxy)-alkyltrichlorosilane (BTS) on a SiO2 substrate. The BTS-OTFTs produced a threshold voltage of -0.50±0.11 V, a mobility of 0.12±0.05 cm2 V-1 s-1, and a on/off current ratio of (1.87±1.22)×102. The second type of gate dielectric used self-grown Al2O3, which was directly grown on a pre-existing Al gate electrode by oxygen plasma process. The self-grown Al2O3-OTFTs exhibited a mobility of 0.12±0.015 cm2 V-1 s1, a threshold voltage of -1.18±0.027 V, and an on/off current ratio of (8.76±5.3)×103. In particular, as the Al2O3 layer is directly grown on a pre-existing Al gate electrode, an additional patterning process for the gate dielectric is not necessary; thus, the fabrication process is simplified. Furthermore, the process is a low temperature, dry process, thereby allowing for low cost fabrications and flexible applications.