Performance Analysis of 60-nm Gate-Length III–V InGaAs HEMTs: Simulations Versus Experiments

Abstract

An analysis of recent experimental data for high-performance In0.7Ga0.3As high electron mobility transistors (HEMTs) is presented. Using a fully quantum mechanical, ballistic model, we simulate In0.7Ga0.3As HEMTs with gate lengths of LG = 60nm, 85, and 135 nm and compare the result to the measured I-V characteristics including draininduced barrier lowering, sub-threshold swing, and threshold voltage variation with gate insulator thickness, as well as on-current performance. To first order, devices with three different oxide thicknesses and channel lengths can all be described by our ballistic model with appropriate values of parasitic series resistance. For high gate voltages, however, the ballistic simulations consistently overestimate the measured on-current, and they do not show the experimentally observed decrease in on-current with increasing gate length. With no parasitic series resistance at all, the simulated on-current of the LG = 60 nm device is about twice the measured current. According to the simulation, the estimated ballistic carrier injection velocity for this device is about 2.7 x 10^7 cm/s. Because of the importance of the semiconductor capacitance, the simulated gate capacitance is about 2.5 times less than the insulator capacitance. Possible causes of the transconductance degradation observed under high gate voltages in these devices are also explored. In addition to a possible gate-voltage dependent scattering mechanism, the limited ability of the source to supply carriers to the channel, and the effect of nonparabolicity are likely to play a role. The drop in on-current with increasing gate length is an indication that the devices operate below the ballistic limit.