Gate Dielectric Thickness Research Articles

High on/off current ratio in ballistic CNTFETs based on tuning the gate insulator parameters for different ambient temperatures

A theoretical study is presented on the on/off current ratio limits for a ballistic coaxially-gated carbon nanotube field effect transistor (CNTFET) with highly doped source/drain regions. Based on changes in gate insulator dielectric constant and thickness, the current ratio has been estimated at different ambient temperatures. Decreasing the gate insulator thickness after a certain value around 3 nm causes the current ratio to degrade drastically. Although the higher dielectric constant values have a fair effect on current ratio, this effect could be suppressed when the device with a low gate insulator thickness works at a low ambient temperature. The simulation results also show that the temperature drastically degrades the current ratio value; whereas in a certain range of ambient temperature, tuning the values of gate insulator thickness and dielectric constant could be very helpful. In this way, the optimum values of gate insulator thickness and dielectric constant are identified to offer the highest on/off current ratio of the device.

GIDL in Doped and Undoped FinFET Devices for Low-Leakage Applications

Investigation of gate-induced drain leakage (GIDL) in thick-oxide dual-gate doped- and undoped-channel FinFET devices through 3-D process and device simulations is presented. For a given gate length (LG) and gate dielectric thickness, the placement and grading of the drain junction and the channel doping are shown to have a tremendous impact on GIDL. Suppression of GIDL by as much as two orders of magnitude can be realized by formation of steep underlapped junctions for both doped- and undoped-channel devices. The prospect of low leakage levels in doped-channel high- VT FinFETs makes them suitable for memory cell applications.

Decomposition of On-Current Variability of nMOS FinFETs for Prediction Beyond 20 nm

ON-current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) variability is comprehensively investigated for fin-shaped FETs (FinFETs) by measurement-based analysis. Variation sources of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> are successfully extracted as independent contributions of threshold voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> , transconductance G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> , and parasitic resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">para</sub> . As well as V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> variability, G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> variation exhibits a linear relationship in the Pelgrom plot. However, the G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> variation is not reduced with scaling the gate dielectric thickness unlike the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> variation. Perspective for 14-nm FinFETs represents that the G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> variation will be the dominant I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> variation source. A solution to reduce the G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> variation for the FinFET is also proposed.

Modeling of a vertical tunneling graphene heterojunction field-effect transistor

Vertical tunneling field-effect-transistor (FET) based on graphene heterojunctions with layers of hBN is simulated by self-consistent quantum transport simulations. It is found that the asymmetric p-type and n-type conduction is due to work function difference between the graphene contact and the tunneling channel material. Modulation of the bottom-graphene-contact plays an important role in determining the switching characteristic of the device. Due to the electrostatic short-channel-effects stemming from the vertical-FET structure, the output I-V characteristics do not saturate. The scaling behaviors the vertical-FET as a function of the gate insulator thickness and the thickness of the tunneling channel material are examined.

Influence of density inhomogeneity on the quantum capacitance of graphene nanoribbon field effect transistors

A semi-analytical model for the capacitance–voltage characteristics of graphene nanoribbon field-effect transistors (GNR-FETs), in the quantum capacitance limit, is presented. The model incorporates the presence of electron–hole puddles induced by local potential fluctuations assuming a Gaussian distribution associated with these puddles. Our numerical results show that the multi-peaks in the non-monotonic quantum capacitance–voltage characteristics are broadened as the potential fluctuation strength increases and the broadening effect is much more pronounced in wide GNRs. The influence of both gate-insulator thickness and dielectric constant scaling on the total gate-capacitance characteristics is also explored. Gate capacitance has non-monotonic behavior with ripples for thin gate-insulators. However, as we go beyond the quantum capacitance limit by increasing insulator thickness or decreasing dielectric constant, the ripples are suppressed and smooth monotonic characteristics are obtained.

Design and Characterization of Plasmonic Terahertz Wave Detectors Based on Silicon Field-Effect Transistors

We report the first implementation of a modeling and simulation environment for the plasmonic terahertz (THz) detector based on the silicon (Si) field-effect transistor (FET) with a technology computer-aided-design (TCAD) platform. The nonresonant plasmonic behavior has been modeled by introducing a quasi-plasma electron box as a two-dimensional electron gas (2DEG) in the channel region. The alternate-current (AC) signal as an incoming THz wave radiation successfully induced a direct-current (DC) drain-to-source voltage as a detection signal in the broadband sub-THz frequency regime. The simulated dependences of photoinduced DC detection signals on structural parameters such as gate length and dielectric thickness confirmed the operation principle of the nonresonant plasmonic THz detector in the Si FET structure. We evaluated the design specifications of THz detectors considering both responsivity and noise equivalent power (NEP) as the typical performance metrics. The proposed methodologies provide the physical design platform for developing novel plasmonic THz detectors operating in the nonresonant detection mode.

Cross characterization of ultrathin interlayers in HfO2 high-k stacks by angle resolved x-ray photoelectron spectroscopy, medium energy ion scattering, and grazing incidence extreme ultraviolet reflectometry

In order to miniaturize metal oxide semiconductor field effect transistors even further and improve their performance, channel lengths and gate dielectric thicknesses must be decreased. Traditionally deployed SiO2 dielectrics face the difficulty of excessive leakage current and must be replaced by alternative (high-k) materials with larger dielectric permitivitties and smaller equivalent oxide thicknesses. A current focus of the industry is studying thin films of HfO2 because they are a main candidate for the next generation of gate dielectrics. Measuring the depth profiles of the constituents of these layered systems is instructive in that it provides information about the thicknesses of the layers and the degree of intermixing between them. Here we demonstrate the use of a novel characterization technique, grazing incidence extreme ultraviolet reflectometry (GIXUVR), which utilizes short wavelength radiation from non-synchrotron sources to measure the depth profile of such thin-film structures. Depth profiles of samples from the same wafers were also measured using angle resolved x-ray photoelectron spectroscopy, medium energy ion scattering, and synchrotron GIXUVR. These measurements show the compatibility and complementarity of the results. The benefits of GIXUVR are the short measuring time (on the order of milliseconds to seconds), as well as high thickness, density, and material sensitivity due to a very efficient interaction of extreme ultraviolet light with matter.

Investigation on the relationship between channel resistance and subgap density of states of amorphous InGaZnO thin film transistors

The demand for amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) has increased due to their transparent properties. In this paper, we report on the relationship between the subgap density of states (DOS), field-effect mobility (μFE), and unit channel length resistance (rch) on the electrical properties of a-IGZO TFTs. The three tested structures had the same channel width/length and gate insulator thickness with different gate insulator materials, SiNX, SiOX, and SiOX/SiNX. Compared to TFTs with low subgap DOS levels, TFTs with high subgap DOS levels have low μFE values due to the relatively large rch values.

Array Test Structures for Gate Dielectric Integrity Measurements and Statistics

An array test structure for highly parallelized stressing and measurements of ultrathin MOS gate dielectrics is presented. The array test structure consisting of thousands of NMOS devices under test (DUTs) provides a large and significant statistical base for analysis of dielectric breakdown and the stress induced degradation of transistor parameters. The test array has been fabricated in a standard mixed-mode 130 nm CMOS technology. As such technologies offer both thin and thick gate dielectrics for MOS transistors, different gate dielectric thicknesses have been chosen for DUTs and digital control logic which gives the possibility to stress the DUTs with high gate voltages and prevent the control logic from degradation.

(Invited) On-Current Variability Sources of FinFETs: Analysis and Perspective for 14nm-Lg Technology

On-current (Ion) variability in FinFETs is comprehensively investigated with regard to contributions of three independent sources, namely, threshold voltage (Vt), parasitic resistance (Rpara) and trans-conductance (Gm) variations. Origins of the Vt and Rpara variations are further analyzed. The Gm variation exhibits a linear relationship in Pelgrom plot as well as the Vt variation, and is not reduced with scaling the gate dielectric thickness unlike the Vt variation. Using the scalability data for the variation components, perspective of the Ion variability for 14-nm FinFETs reveals that the Gm variation will be the dominant Ion variation source. A solution to reduce the Gm variation for FinFETs is also proposed.

Analysis of temperature and wave function penetration effects in nanoscale double-gate MOSFETs

Wave function penetration has significant impact on nanoscale devices having ultrathin gate oxide. Although wave function penetration effects on ballistic drain current and capacitance-voltage characteristics in nanoscale devices have been reported in literature, to the best of the authors’ knowledge, effects of temperature on drain current incorporating with and without wave function penetration are yet to be studied. In this work, the impacts of temperature, gate dielectric and film thickness in wave function penetration on ballistic drain current of nanoscale double-gate (DG) MOSFETs are presented. The effects are observed using two-dimensional self-consistent solution of Schrödinger and Poisson equations. It has been obtained that temperature effect on drain current is greatly dependent on silicon surface orientation. Drain current of DG MOSFETs fabricated on $$\langle110\rangle$$ surface is more sensitive to temperature compared to $$\langle001\rangle$$ surface. This has been obtained for both the cases with and without incorporating wave function penetration in silicon–gate oxide interface. Electrostatics behind this phenomenon has been explained from the transmission probability of electrons from source to drain which is largely influenced by temperature on $$\langle110\rangle$$ surface compared to $$\langle001\rangle.$$ Moreover, the transmission coefficient is significantly affected by wave function penetration in $$\langle110\rangle \hbox{ than }\langle001\rangle$$ surface. Both these demonstrate greater sensitivity of temperature and wave function penetration in $$\langle110\rangle$$ silicon surface orientation compared to $$\langle001\rangle.$$ Furthermore, gate dielectric with lower conduction band offset and device scaling with thin channel thickness tend to exhibit greater impact of wave function penetration.

Optical modeling and experimental verification of light induced phenomena in In-Ga-Zn-O thin film transistors with varying gate insulator thickness

A simple optical model based on the transfer matrix method was used to simulate photon absorption in oxide semiconductor systems with varying insulator thickness in the thin film transistor (TFT) structure. For comparison with actual experimental results, hole current was measured in transparent metal/semiconductor/insulator/metal capacitor stacks under light illumination, and the threshold voltage shift under negative bias illumination stress conditions was also measured in the TFT structure. In each structure, experimental data showed variance as the insulator thickness changed, and these results agreed well with the simulations. The results showed that light interference in multi-layered devices has a crucial influence on the reliability of them under illumination and that they should be considered when designing systems that work under these conditions. The accuracy of the simulations suggests they can be implemented to minimize instability issues in oxide TFTs for display.

Effect of gate length and dielectric thickness on ion and fluid transport in a fluidic nanochannel

We have simulated the effect of gate length and dielectric thickness on ion and fluid transport in a fluidic nanochannel with negative surface charge on its walls. A short gate is unable to induce significant cation enrichment in the nanochannel and ion current is controlled mostly by cation depletion at positive gate potentials. The cation enrichment increases with increasing gate length and/or decreasing dielectric thickness due to higher changes induced in the surface charge density and zeta-potential. Thus, long gates and thin dielectric layers are more effective in controlling ion current. The model without Navier-Stokes equations is unable to correctly predict phenomena such as cation enrichment, increase in channel conductivity, and decreasing electric field. Body force and induced fluid velocity decrease slowly and then rapidly with gate potentials. The effectiveness of ion current control by a gate reduces with increasing surface charge density due to reduced fractional change in zeta-potential.

Study of Carbon Nanotube Field Effect Transistors Performance Based on Changes in Gate Parameters

Carbon nanotubes are known as an interesting material to be used in the next generations of electronic technology, especially at nano regime. Nowadays, carbon nanotube field effect transistor or CNTFET is one of the promising devices for future electronic applications. A CNTFET which uses carbon nanotube as channel or source/drain region is the most promising candidate for replacing the current silicon transistor technology. The study of modern manufacturing approach and impact of device parameters on its performance is one of the important research fields in nanoelectronics. In this paper we study some aspects of changes in gate parameters at different channel diameters. This paper shows that for small values of diameter, increasing the dielectric constant of gate insulator doesn't help to improve the performance as value of dielectric constant of gate insulator reaches a certain amount. Also, increasing the oxide thickness of gate insulator doesn't always decrease transistor performance. For high diameter values, increasing the thickness up to a certain value improves the transistor performance.

Effect of gate dielectric scaling in nanometer scale vertical thin film transistors

A short channel vertical thin film transistor (VTFT) with 30 nm SiNx gate dielectric is reported for low voltage, high-resolution active matrix applications. The device demonstrates an ON/OFF current ratio as high as 109, leakage current in the fA range, and a sub-threshold slope steeper than 0.23 V/dec exhibiting a marked improvement with scaling of the gate dielectric thickness.

(Invited) Effect of Al2O3/InGaAs Interface on Channel Mobility

In this paper, we discuss the effect of Al2O3/InGaAs interface on In0.53Ga0.47As quantum-well MOSFET channel mobility. We fabricated Al2O3 (gate dielectric)/In0.53Ga0.47As-In0.52Al0.48As (barrier)/In0.53Ga0.47As (channel) structures to study effects of gate dielectric thickness and barrier thickness on channel carrier mobility. Hall measurements were used to examine the mobility. The mobility was invariant with varying gate dielectric thickness, suggesting that charges trapped within the Al2O3 do not affect mobility significantly. The mobility varies with varying barrier thickness suggesting that Al2O3/In0.53Ga0.47As interfacial charges affect mobility. In our case, when the barrier thickness <5 nm, the mobility is dominated by coulomb scattering from interfacial charges; when the barrier thickness >5 nm, the mobility is dominated by internal phonon scattering. A model was developed to fit the experimental data and this model could be used to sample MOSFET designs that are limited by phonon scattering and gate dielectric/barrier layer interfacial charge density.

Analytical Modeling of Graphene Nanoribbon Schottky Diodes Using Asymmetric Contacts

This paper presents graphene nanoribbon (GNR) Schottky diode through an analytical approach. To achieve an analytical relation for channel current, first an analytical equation for potential distribution within the GNR is offered. Then by using the WKB approximation, transmission probability through Schottky barriers is derived. Finally the channel current is analytically achieved, which is a function of physical and electrical parameters including gate insulator thickness, Schottky barrier height, drain bias voltage, gate bias voltage, GNR width, and subband number. To get a rectification behavior of presented device, two different metals have been considered at the two ends of a p-type semiconducting GNR resulting in asymmetric contacts. The effect of different parameters such as gate bias voltage, GNR width, and contact metals on the rectification behavior is investigated. We demonstrate that the rectification characteristic, threshold voltage, reverse saturation current, and reverse turn-on voltage can be tuned through the use of these parameters. The derived analytical current well describes the rectifying behavior of presented GNR Schottky diode.

Impact of gate poly doping and oxide thickness on the N- and PBTI in MOSFETs

We study n- and pMOS devices with 3.2–30nm thick SiON or SiO2 gate dielectrics and n++ or p++ doped polysilicon gates to identify the type and energetic location of defects created through bias temperature stress. The results clearly indicate a dependence of the type of BTS induced defects on the stress polarity and the gate poly doping. If holes are provided from the p++ poly gate and the gate dielectric is sufficiently thin, NBTI-type donor-like defects may occur even under positive bias stress conditions. For devices with sufficiently thick dielectrics or n++ poly gated devices, holes are absent during PBTI stress and acceptor-like defects are created.

Gate-Field Engineering and Source/Drain Diffusion Engineering for High-Performance Si Wire GAA MOSFET and Low-Power Strategy in Sub-30-nm-Channel Regime

This paper reconsiders the design methodology of the short-channel gate-all-around (GAA) silicon-on-insulator (SOI) MOSFET and proposes an advanced concept that offers enhanced performance. The new ideas raised herein are based on gate-field engineering and source and drain (S/D) diffusion engineering. The validity of the proposal is demonstrated by device simulations. Covering the junction of a Si wire body with a relatively thick gate insulator raises the carrier density of low-doped S/D diffusion regions, resulting in a drastic reduction in the parasitic resistance (that has, up to now, hindered performance enhancement) as well as the suppression of short-channel effects due to the effective extension of channel length; it is also demonstrated that this merit can be expected even for narrow highly doped S/D diffusion regions with abrupt junctions. The simulation results suggest that 15-nm- and 20-nm-channel GAA SOI MOSFETs with the abrupt junction will be promising if the device has a body cross section of 10 nm × 10 nm and a thick insulator covers the junction. On the other hand, since it is demonstrated that the proposed GAA device must have long and graduated S/D diffusion regions in order to achieve the expected one-order-lower standby power consumption, a loss of drivability has to be accepted. However, it is shown that drivability can be improved by slightly expanding the cross section of S/D diffusion regions without seriously impacting the area penalty.

TiN/HfSiON for Analog Applications of nMuGFETs

This work presents an analysis of the impact of the implementation of a hafnium gate dielectric on triple-gate structures for analog applications. A reduced Early voltage VEA is observed for the hafnium dielectric. This was attributed to a slightly higher physical gate dielectric thickness observed on HfSiON dielectric that could be leading to a increasing on the horizontal electric field contribution on the drain current. As a result, lower intrinsic voltage gain was observed for high-k dielectrics when compared with a SiON gate insulator.