Gate Field Plate Research Articles

Influence of surface states on the voltage robustness of AlGaN/GaN HFET power devices

In this work we discuss the influence of the donor-like surface state density (SSD) on leakage currents and the breakdown voltages of AlGaN/GaN heterostructure field-effect transistors (HFET) at high temperature reverse bias (HTRB) step stress. A method to extract charges at the surface by high voltage capacitance voltage (HV–CV) profiling of the gate–drain diode of a HFET is presented. Two samples with different surface passivation are compared. The SSD of the first sample is found to be similar to the polarization charge, whereas it is elevated by a factor of three on the second sample. The influence of the SSD on the electric field is investigated with electroluminescence (EL). The elevated SSD of the second sample engenders severe deficiencies in robustness found in the HTRB. The stress data, the simulation model and the images of EL indicate that the catastrophic failure arises in the dielectric underneath the gate field plate (GFP).

Reverse blocking enhancement of drain field plate in Schottky-drain AlGaN/GaN high-electron mobility transistors

In this paper, we present the combination of drain field plate (FP) and Schottky drain to improve the reverse blocking capability, and investigate the reverse blocking enhancement of drain FP in Schottky-drain AlGaN/GaN high-electron mobility transistors (HEMTs). Drain FP and gate FP were employed in a two-dimensional simulation to improve the reverse blocking voltage (VRB) and the forward blocking voltage (VFB). The drain-FP length, the gate-FP length and the passivation layer thickness were optimized. VRB and VFB were improved from −67 V and 134 V to −653 V and 868 V respectively after optimization. Simulation results suggest that the combination of drain FP and Schottky drain can enhance the reverse blocking capability significantly.

A RESURF-Enhanced p-Channel Trench SOI LDMOS With Ultralow Specific on-Resistance

A low specific on-resistance ( \(R_{{{\rm \mathrm{{\scriptstyle ON}},sp}}}\) ) silicon-on-insulator (SOI) p-channel LDMOS (pLDMOS) with an enhanced reduced surface field (RESURF) effect and self-shielding effect of the back-gate (BG) bias is proposed and investigated. It features an oxide trench and the p-drift region surrounding the trench, which is built on the n-SOI layer. In the OFF-state, first, the extended trench gate also acts as a gate field plate; second, the p-drift and the n-SOI layer forms a folded RESURF structure. Both increase the doping dose of the p-drift and modulate electric field (E-field) distribution; third, the oxide trench not only reduces the device pitch but also enhances the E-field strength. All of them result in a low \(R_{\rm {\scriptstyle {ON,SP}}}\) and a high breakdown voltage (BV) with a reduced device pitch. The free charges induced on the SOI/buried oxide (BOX) interface not only enhance the E-field strength in the BOX but also effectively shield the influence of BG bias effect in a wide range. The proposed pLDMOS achieves state-of-the-art improvement in the tradeoff between BV and \(R_{\rm {\scriptstyle {ON,SP}}}\) . Compared with the p-top SOI pLDMOS, the proposed device reduces the \(R_{\rm {\scriptstyle {ON,SP}}}\) by 79% at the same BV. A strong immunity to the BG bias effect is demonstrated and analyzed in detail.

Investigation on Electrical Degradation of High Voltage nLDMOS After High Temperature Reverse Bias Stress

The breakdown voltage (BV) and on resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dson</sub> ) degradation of the 700-V n-type single-RESURF lateral double-diffused MOS (nLDMOS) after high-temperature reverse bias (HTRB) stress have been investigated in this work. A detail analysis that shows good agreement with the experiments is proposed based on electrostatic force microscope (EFM) testing, charge-pumping testing, and TCAD simulations. The BV degradation is caused by the generated positive ions from the device surface under HTRB stress. Not only the BV decreases but also the breakdown position migrates up from the body region to the surface region below the gate field plate of the device. Interface states are generated due to the hot carriers injected into the gate oxide and the field oxide below the gate field plate, which is the reason for the R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dson</sub> degradation. In order to avoid the degradation, reducing the drift doping is one of the effective methods, although it will sacrifice the conduction capability. The tradeoff between robustness and conduction capability is also presented.

Impact of Bias and Device Structure on Gate Junction Temperature in AlGaN/GaN-on-Si HEMTs

The thermal impact of device bias-state and structures (such as source connected field plates, gate-pitch, back-vias, and number of gate fingers) in AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) are measured using gate metal resistance thermometry (GMRT). The technique characterizes the thermal response of device gate metallization to determine the gate-epilayer junction temperature (Tj), which is directly influenced by the channel heat source due to its close proximity. It is found that low gate leakage levels in GaN HEMTs make them favorable candidates for GMRT. Bias-dependent self-heating, independent of power dissipation, is observed in the devices. Therefore, Tj of different device configurations are compared at constant bias state, as well as constant power density (3.75 W/mm) to improve accuracy. Tj reduction is observed at high drain bias due to the migration of the channel heat source toward the gate field plate edge. This provides independent experimental validation for a reported electrothermal model [7]. A 3-D thermal finite element method model is presented, which simulates measured Tj rise to within ~6% across a range of device configurations and operating conditions. This is ultimately made possible upon implementation of a thermal boundary resistance layer and extraction of its temperature response using GMRT data.

Effects of Gate Field Plates on the Surface State Related Current Collapse in AlGaN/GaN HEMTs

During off-state, the influence of surface-trapped electron charges induced by high-field stress near the gate electrode of AlGaN/GaN power high-electron mobility transistor devices causes a reduction in two-dimensional electron gas (2DEG) carrier density at the heterointerface. In a pulse turn-on operation, the weakened 2DEG channel results in a higher on-state conduction resistance during the transient, known as the current collapse phenomenon. The phenomenon increases the switching loss by a higher on-state resistance and prolonged turn-on transition time, thus limits the device operating frequency range. In this paper, such a phenomenon is modeled, analyzed by Sentaurus TCAD simulation, and verified by the laboratory measurement data, with the emphasis on the influence of field plates toward the current collapse. The spatial distributions of trapped electrons and excess free electrons along the AlGaN surface are modeled and analyzed to arrive at the quantitative relationships among the trapped electron density, on-resistance increase, and the electric field distribution which provide a reliable criterion for current collapse reduction. It was found that, with a proper field plate design, it is possible to achieve an improvement on transient on-state resistance and the current recovery time.

Influence of a drain field plate on the forward blocking characteristics of an AlGaN/GaN high electron mobility transistor

In this paper, the influence of a drain field plate (FP) on the forward blocking characteristics of an AlGaN/GaN high electron mobility transistor (HEMT) is investigated. The HEMT with only a gate FP is optimized, and breakdown voltage VBR is saturated at 1085 V for gate—drain spacing LGD ≥ 8 μm. On the basis of the HEMT with a gate FP, a drain FP is added with LGD = 10 μm. For the length of the drain FP LDF ≤ 2 μm, VBR is almost kept at 1085 V, showing no degradation. When LDF exceeds 2 μm, VBR decreases obviously as LDF increases. Moreover, the larger the LDF, the larger the decrease of VBR. It is concluded that the distance between the gate edge and the drain FP edge should be larger than a certain value to prevent the drain FP from affecting the forward blocking voltage and the value should be equal to the LGD at which VBR begins to saturate in the first structure. The electric field and potential distribution are simulated and analyzed to account for the decrease of VBR.

Current Collapse Suppression by Gate Field-Plate in AlGaN/GaN HEMTs

Current collapse measurements have been performed for AlGaN/GaN high-electron-mobility transistors having identical breakdown voltages but with different field plate (FP) lengths. The results indicated that applying more positive ON-state gate biases resulted in pronounced recovery in the dynamic ON-resistance for the FP device, whereas no gate-bias effects were observed for the device without FP. The mechanism responsible for the reduced current collapse by FP is proposed, in which the key role is played during ON-state by the quick field-effect recovery of partial channel depletion caused by electron trapping at AlGaN surface states between gate and drain.

Field plate structural optimization for enhancing the power gain of GaN-based HEMTs

A novel source-connected field plate structure, featuring the same photolithography mask as the gate electrode, is proposed as an improvement over the conventional field plate (FP) techniques to enhance the frequency performance in GaN-based HEMTs. The influences of the field plate on frequency and breakdown performance are investigated simultaneously by using a two-dimensional physics-based simulation. Compared with the conventional T-gate structures with a field plate length of 1.2 μm, this field plate structure can induce the small signal power gain at 10 GHz to increase by 5-9.5 dB, which depends on the distance between source FP and dramatically shortened gate FP. This technique minimizes the parasitic capacitances, especially the gate-to-drain capacitance, showing a substantial potential for millimeter-wave, high power applications.

Localization of off-stress-induced damage in AlGaN/GaN high electron mobility transistors by means of low frequency 1/f noise measurements

The location of the time dependent degradation in OFF-state stressed AlGaN/GaN high electron mobility transistors is studied using low frequency 1/f noise measurements, with additional electroluminescence analysis. The gate bias dependence of the 1/f noise is shown to be a powerful tool to illustrate that in addition to the gate edge breakdown, progressive time-dependent trap generation occurs underneath the gate area, possibly extending in the gate-drain access region due to the electric field peak associated with the gate field plate.

Delay Time Analysis of Graded Gate Field-Plate AlGaN/GaN High Electron Mobility Transistors Using Monte Carlo Simulation

The mechanisms of delay time generation in graded gate field-plate (FP) AlGaN/GaN high electron mobility transistors (HEMTs) are investigated using Monte Carlo simulation. The graded gate FP suppresses the increase in the maximum electric field with the drain voltage by extending the high electric field area toward the drain. However, in addition to the FP capacitance delay time caused by the capacitance between the FP and the channel, the extension of the high electric field area itself increases the electron accumulation delay time caused by electron occupation of the upper valleys. Eventually, as the FP angle increases, the intrinsic cutoff frequency fT decreases.

Bias-stress-induced trapping effect of high-voltage field-plated AlGaN/GaN-on-Si heterostructure FETs

AlGaN/GaN heterostructure field effect transistors (HFETs) with a gate field plate were fabricated on GaN-on-Si substrates. Devices demonstrated high breakdown voltages over 500 V for high-voltage switching operation. We applied a DC stress under on-state and off-state conditions to investigate the degradation characteristics. Degradations of the output and the transfer characteristics were observed after stress tests and recovered after 10 days in ambient storage. The electron trapping effect played a major role in the observed degradations. We also observed a correlation between the field-plate length and the degradation. The technology computer aided design (TCAD) simulation indicated that this dependence could be attributed to a change in the electric field distribution in the channel that depended on the field-plate dimension.

Dynamic Characterizations of AlGaN/GaN HEMTs With Field Plates Using a Double-Gate Structure

A novel double-gate AlGaN/GaN HEMT, in which an additional top-gate covers the adjacent regions of a normal gate, was proposed and fabricated for the first time to compare the dynamic characteristics of AlGaN/GaN HEMTs with a source field plate (SFP) and a gate field plate (GFP). During the dynamic characterization, the device was configured in two operation modes: One is the SFP mode with the top gate biased at 0 V, and the other is the GFP mode applying the gate pulse signal on the top gate at the same time. Compared with an AlGaN/GaN HEMT without field plates, both GFP and SFP much improve the dynamic performances. Compared with the SFP, the GFP shows better dynamic performances with a ~ 34% reduction of switch-on delay time and ~ 6% reduction of dynamic on-state resistance. Studying the dynamic characteristics and applying negative voltage on the top gate during the off state, the mechanism differences between the GFP and the SFP are discussed in detail.

Radiative inter-valley transitions as a dominant emission mechanism in AlGaN/GaN high electron mobility transistors

We report on electroluminescence (EL) emission from AlGaN/GaN high electron mobility transistors (HEMTs). Intensity maxima at the drain-side edge of the gate foot and at the drain-side edge of the gate field plate are observed. To relate the EL intensity profile to the electric field along the channel, 2D device simulations have been performed at different drain biases. The dependences of both EL maxima on the electric field reveal a threshold which closely correlates with the electric field strength at which a transfer of conduction band electrons from the zone centre minimum to satellite valleys sets in. We further analyze the dependence of the EL spectra on the drain voltage. The obtained results strongly suggest that the EL emission observed in AlGaN/GaN HEMTs is dominated by radiative inter-valley electron transitions.

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer (TSL) with linear variable doping (LVD) and further research on the TSL LVD with a multiple step field plate (MSFP), a breakdown voltage (BV) model is proposed and experimentally verified in this paper. With the two-dimensional Poisson equation of the silicon on insulator (SOI) device, the lateral electric field in drift region of the thin silicon layer is assumed to be constant. For the SOI device with LVD in the thin silicon layer, the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field (ENDIF), from which the reduced surface field (RESURF) condition is deduced. The drain in the centre of the device has a good self-isolation effect, but the problem of the high voltage interconnection (HVI) line will become serious. The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device. Based on this model, the TSL LVD SOI n-channel lateral double-diffused MOSFET (nLDMOS) with MSFP is realized. The experimental breakdown voltage (BV) and specific on-resistance (Ron,sp) of the TSL LVD SOI device are 694 V and 21.3 Ω-mm2 with a drift region length of 60 μm, buried oxide layer of 3 μm, and silicon layer of 0.15 μm, respectively.

High-voltage AlGaN/GaN HFETs by using graded gate field plates

High-voltage AlGaN/GaN heterostructure field-effect transistors (HFETs) with graded gate field-plate (FP) structures were fabricated to investigate the effectiveness of a linearly graded FP structure on current collapse. To improve the reproducibility of the FP structure manufacturing process, a simple process for a linearly graded SiO2 profile formation was developed. A HFET with a 23°-angle FP exhibited a significantly decreased on-resistance increase ratio of 1.16 after application of a drain bias of 600 V.

Analysis of backside-electrode and gate-field-plate effects on buffer-related current collapse in AlGaN/GaN high electron mobility transistors

Two-dimensional transient analysis of gate-field-plate AlGaN/GaN high electron mobility transistors with a backside electrode is performed by considering a deep donor and a deep acceptor in a buffer layer. Effects of introducing a field plate and a backside electrode on buffer-related lag and current collapse are studied. It is shown that gate field plate introduction is effective in reducing lag and current collapse when the acceptor density in the buffer layer is high. On the other hand, backside electrode introduction is shown to be effective in reducing drain lag and current collapse, particularly when the acceptor density in the buffer layer is relatively low, because the fixed potential at the backside electrode reduces electron injection into the buffer layer and the resulting trapping effects.

SiNx Prepassivation of AlGaN/GaN High-Electron-Mobility Transistors Using Remote-Mode Plasma-Enhanced Chemical Vapor Deposition

The surface of AlGaN/GaN high-electron-mobility transistors (HEMTs) tends to be easily damaged during device fabrication, especially during high-temperature annealing. In order to resolve this problem, a prepassivation process was developed using remote-mode plasma-enhanced chemical vapor deposition (RPECVD) systems. It is important in the prepassivation process to protect the region under the gate during high-temperature ohmic annealing and utilize a low-damage SiNx etching process to minimize any surface damage. It was observed that the DC characteristics were significantly improved and the current collapse phenomenon was markedly suppressed for AlGaN/GaN HEMTs by employing the prepassivation process proposed in this work in comparison with a conventional process. According to the experimental results, the prepassivation process coupled with a gate field plate successfully suppressed the current collapse phenomenon in AlGaN/GaN HEMTs. RF output power densities of 6.9 W/mm at 2.3 GHz and >8.9 W/mm at 4 GHz were achieved for AlGaN/GaN HEMTs on Si and SiC substrates, respectively.

Design of AlGaN/GaN HEMTs employing mesa field plate for breakdown voltage enhancement

We proposed the AlGaN/GaN high electron mobility transistors (HEMTs) employing the mesa field plate and carried out the detailed numerical simulation of device operation using ISE-TCAD. The reduction of peak electric field is required to achieve the high breakdown voltage of AlGaN/GaN HEMTs. Proposed AlGaN/GaN HEMT with both gate and mesa field plates simultaneously reduced the electric field concentration at the gate and the drain edge by decreasing the potential gradient along the 2-DEG channel. As the peak electric field at the drain edge was decreased, the breakdown voltage was increased by 66% compared with the AlGaN/GaN HEMT with the gate field plate only. The breakdown voltage could be increased without sacrificing any other forward characteristics due to the SiO2 passivation layer.

Breakdown Enhancement of AlGaN/GaN HEMTs on 4-in Silicon by Improving the GaN Quality on Thick Buffer Layers

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We have achieved a 9- <formula formulatype="inline"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula>-thick AlGaN/GaN high-electron mobility transistor (HEMT) epilayer on silicon using thick buffer layers with reduced dislocation density <formula formulatype="inline"><tex Notation="TeX">$(D_{D})$</tex></formula>. The crack-free 9- <formula formulatype="inline"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula>-thick epilayer included 2- <formula formulatype="inline"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula> i-GaN and 7- <formula formulatype="inline"><tex Notation="TeX">$ \mu\hbox{m}$</tex></formula> buffer. The HEMTs fabricated on these devices showed a maximum drain–current density of 625 mA/mm, transconductance of 190 mS/mm, and a high three-terminal OFF breakdown of 403 V for device dimensions of <formula formulatype="inline"><tex Notation="TeX">$L_{g}/W_{g}/L_{\rm gd} = \hbox{1.5/15/3} \ \mu\hbox{m}$</tex> </formula>. Without using a gate field plate, this is the highest <formula formulatype="inline"><tex Notation="TeX">$BV$</tex> </formula> reported on an AlGaN/GaN HEMT on silicon for a short <formula formulatype="inline"><tex Notation="TeX">$L_{\rm gd}$</tex> </formula> of 3 <formula formulatype="inline"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula>. A very high <formula formulatype="inline"><tex Notation="TeX">$BV$</tex></formula> of 1813 V across 10- <formula formulatype="inline"><tex Notation="TeX">$\mu \hbox{m}$</tex></formula> ohmic gap was achieved for i-GaN grown on thick buffers. As the thickness of buffer layers increased, the decreased <formula formulatype="inline"><tex Notation="TeX">$D_{D}$</tex></formula> of GaN and increased resistance between surface electrode and substrate yielded a high breakdown. </para>