A RESURF-Enhanced p-Channel Trench SOI LDMOS With Ultralow Specific on-Resistance

Abstract

A low specific on-resistance ( \(R_{{{\rm \mathrm{{\scriptstyle ON}},sp}}}\) ) silicon-on-insulator (SOI) p-channel LDMOS (pLDMOS) with an enhanced reduced surface field (RESURF) effect and self-shielding effect of the back-gate (BG) bias is proposed and investigated. It features an oxide trench and the p-drift region surrounding the trench, which is built on the n-SOI layer. In the OFF-state, first, the extended trench gate also acts as a gate field plate; second, the p-drift and the n-SOI layer forms a folded RESURF structure. Both increase the doping dose of the p-drift and modulate electric field (E-field) distribution; third, the oxide trench not only reduces the device pitch but also enhances the E-field strength. All of them result in a low \(R_{\rm {\scriptstyle {ON,SP}}}\) and a high breakdown voltage (BV) with a reduced device pitch. The free charges induced on the SOI/buried oxide (BOX) interface not only enhance the E-field strength in the BOX but also effectively shield the influence of BG bias effect in a wide range. The proposed pLDMOS achieves state-of-the-art improvement in the tradeoff between BV and \(R_{\rm {\scriptstyle {ON,SP}}}\) . Compared with the p-top SOI pLDMOS, the proposed device reduces the \(R_{\rm {\scriptstyle {ON,SP}}}\) by 79% at the same BV. A strong immunity to the BG bias effect is demonstrated and analyzed in detail.