Impact of Bias and Device Structure on Gate Junction Temperature in AlGaN/GaN-on-Si HEMTs

Abstract

The thermal impact of device bias-state and structures (such as source connected field plates, gate-pitch, back-vias, and number of gate fingers) in AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) are measured using gate metal resistance thermometry (GMRT). The technique characterizes the thermal response of device gate metallization to determine the gate-epilayer junction temperature (Tj), which is directly influenced by the channel heat source due to its close proximity. It is found that low gate leakage levels in GaN HEMTs make them favorable candidates for GMRT. Bias-dependent self-heating, independent of power dissipation, is observed in the devices. Therefore, Tj of different device configurations are compared at constant bias state, as well as constant power density (3.75 W/mm) to improve accuracy. Tj reduction is observed at high drain bias due to the migration of the channel heat source toward the gate field plate edge. This provides independent experimental validation for a reported electrothermal model [7]. A 3-D thermal finite element method model is presented, which simulates measured Tj rise to within ~6% across a range of device configurations and operating conditions. This is ultimately made possible upon implementation of a thermal boundary resistance layer and extraction of its temperature response using GMRT data.