Gate-drain Capacitance Research Articles

A Predictive Algorithm for Crosstalk Peaks of SiC MOSFET by Considering the Nonlinearity of Gate-Drain Capacitance

A predictive algorithm for accurately determining the crosstalk peaks caused by SiC MOSFET s is proposed in this article, which is very important to better design the drive and protect circuits of SiC MOSFET s. Compared to the conventional algorithm of crosstalk peaks, the nonlinearity of gate-drain capacitance ( C gd) is first considered in the proposed algorithm. In detail, the differential expression of the crosstalk peaks is deduced, in which, the main factors affecting crosstalk peaks are all included. Following, the execution flow of the predictive algorithm is provided according to the differential expression. To verify the accuracy of the proposed algorithm with considering the nonlinearity of C gd, the simulation and experiment platforms are established and verified by using Kelvin packaged SiC MOSFET IMZ120R045M1 (1200 V/52 A). The calculation results of the proposed algorithm are compared with the conventional algorithm without considering the nonlinearity of C gd under different working conditions of SiC MOSFET . Finally, the calculation results, the simulation, and experiment results show that the proposed algorithm is effective and has better accuracy. Therefore, the predictive algorithm proposed in this article provides a theoretical reference to better design the drive and protect circuits of SiC MOSFET s.

Robustness to ambipolarity and improvement to HF FOMs of dual-stacked-gate dielectrics underlap heterojunction TFETs

This work presents a new TFET architecture which not only diminishes ambipolar current (IAMB) but also shows high on state current (ION), high ratio of ION to IOFF, and less off-state current (IOFF). Initially, to show the effects on ambipolarity and on- and off-state current, a comparative analysis of transfer characteristics among the proposed, conventional, and the heterojunction (HJ) TFET has been done. The effects of different gate material work functions and gate oxide thicknesses on IAMB for the proposed TFET and the HJ TFET with no underlap are examined. Further, to analyze the effect of ambipolarity in the high-frequency figure of merit (FOM), a comparative analysis on RF parameters such as gate–drain capacitance (Cgd), cutoff frequency (fT), total gate capacitance (Cgg), and the intrinsic time delay (τ) for both of the devices (proposed and HJ TFETs) has been studied.

An ultralow loss 4H-SiC double trenches MOSFET with integrated heterojunction diodes and split gate

A novel ultralow loss 4H-SiC double trenches MOSFET is presented and its mechanism is investigated by simulation. The device features two integrated heterojunction diodes (HJD) consisting of a P-type polycrystalline Silicon and SiC, a trench split gate (SG) and P+ region (PR) beneath the source trench. Both the SG and PR reduce the coupling effect between gate and drain, and transform part of gate-drain capacitance (CGD) into gate-source capacitance (CGS) and drain-source capacitance (CDS). Compared with the conventional trench MOSFET (Con-TMOS) and the HJD trench MOSFET (HJD-TMOS), the proposed double trenches MOSFET with integrated HJDs and SG (HJD-SG-DTMOS) decreases the CGD by 83% and 89%, respectively. Moreover, the integrated HJDs take the place of the parasitic body diode as a freewheel diode, and thus reduce the reverse turn-on voltage. As a result, not only is the reverse turn-on voltage of the proposed device decreased by 69% and 33%, but also the switching loss is reduced by 64% and 49%, compared with those of Con-TMOS and HJD-TMOS, respectively.

New small‐signal extraction method applied to GaN HEMTs on different substrates

In this article, a new extraction technique is proposed to extract the small-signal parameters of gallium nitride (GaN) high electron mobility transistors (HEMTs) on three different substrates namely, Si, SiC, and Diamond. This extraction technique used a single small-signal circuit model to efficiently describe the physical and electrical properties of GaN on different substrates. This technique takes into account any asymmetry between the gate-source and gate-drain capacitances on the asymmetrical GaN HEMT structure, charge-trapping effects, passivation layer inclusion, as well as leakage currents associated with the nucleation layer between the GaN buffer layer and the different substrates. The extracted values were then optimized using the grey wolf optimizer. The proposed technique was demonstrated through a close agreement between simulated and measured S-parameters.

Analytical Model to Study Hard Turn-off Switching Dynamics of SiC mosfet and Schottky Diode Pair

Fast switching transient of SiC mosfet may lead to prolonged oscillations, spurious turn on, large device stress, and high amount of electromagnetic interference generation. For an optimal layout and gate driver design, study of switching dynamics is important. This article presents an analytical model that captures the turn-off switching dynamics of SiC mosfet and SiC Schottky barrier diode (SBD) pair using parameters obtained from device and gate driver datasheets and the values of external circuit parasitics. Unlike linear approximation, a detailed model of channel current is considered that captures the gradual transition from ohmic to saturation region and the transverse electric field effect. A comprehensive model of the transfer capacitance is used and the effect of external gate-drain capacitance is considered. This results in a better estimation of switching transition time, actual loss incurred, (dv/dt), (di/dt), and transient overvoltage. The behavioral simulation and experimental results confirm the accuracy of the presented analytical model over a range of operating conditions for two 1.2-kV discrete SiC mosfet and SBD pairs of different current ratings.

Relative effectiveness of high-k passivation and gate-connected field plate techniques in enhancing GaN HEMT breakdown

Prior work has shown that the OFF-state breakdown voltage, VBR, of AlGaN/GaN high electron mobility transistors (HEMTs) can be raised by just extending the drain end of the gate as a field plate (FP) or a high-k passivation over the AlGaN layer. However, the two techniques have not been compared, and the VBR for which their effectiveness was demonstrated was ≥120 V. High-k passivation avoids the lithography involved in realizing a FP, and the VBR of practical devices can go down to a few 10's of volts. Hence the present work compares the effectiveness of these techniques by TCAD simulations and establishes the following. At VBR of few 10's of Volts, the high-k passivation is much less effective than the FP, e.g. for a device with VBR = 28 V, a 0.7 μm long FP over 0.105 μm thick SiN doubles the VBR to 56 V, whereas even a 0.5 μm thick HfO2 passivation (εr = 20) has almost no effect on VBR. However, such differences between the two techniques reduce progressively as VBR is raised. The differences vanish for VBR ≥ 100 V, for which both techniques can improve the VBR by ≥ 2.5 times. Although focused primarily on breakdown, our work gives quick calculations showing that the high-k passivation has 5 – 10 % higher gate-drain capacitance than the gate-connected FP.

Comparison between [formula omitted] integration and [formula omitted] derivation methods dedicated to fast short-circuit 2D diagnosis for wide bandgap power transistors

This study presents and compares two original high-speed protection circuit methods, namely, ig integration and vgs derivation, against short-circuit types, referred to as, the hard switch fault and fault under load. Since the gate–drain capacitor Cgd of a power device depends on the drain to source voltage vds, it can become an original native sensor to monitor the switching operation and so detect the unwanted vds transition or the absence of the vds transition by monitoring only vgs. The use of only low-voltage monitoring, such as vgs, is an essential step to integrate fast and embedded new detection methods into a low-voltage application-specific integrated circuit gate driver, in particular for wide bandgap power transistors. The Cgd capacitor plays a major part in the two detection methods. The first method is based on dedicated two-dimensional monitoring of the gate charge transferred in a time interval combined with gate voltage monitoring. The second method consists of the reconstruction of the dvgs/dt by means of a capacitive current sensing to provide the vgs derivation combined with the vgs monitoring. Comparison and simulation of the methods based on a C2M0025120D SiC MOSFET device under LTspice™ are made to verify the validity of the methods. In terms of detection speed of the short circuit, a detection time of 200 ns is obtained for both methods. Experimental waveforms based on C3M0120090J SiC MOSFET device were included into LTspiceTM to push furthermore the methods to their limits and validate the approaches. Both methods are easy to design and to integrate. However, the robustness and the speed of detection trade-off of all these methods should be analysed and compared relative to the critical functionalities.

On the Enhanced Miller Capacitance of Source-Gated Thin Film Transistors

An enhanced Miller capacitance effect in the source-gated thin film transistors (SGT) is reported in this work. The gate-drain capacitance ${C}_{\textit {gd}}$ is larger than the gate-source capacitance ${C}_{\textit {gs}}$ , as opposed to the capacitance properties in conventional thin film transistors (TFT). By numerical device simulations the enhanced ${C}_{\textit {gd}}$ is attributed to the channel capacitance with a larger partition of channel charge to the drain side. When used as a driving transistor in active matrix display pixels, SGT shows an overshoot current imposing on the light-emitting device. Reducing the operation voltage ${V}_{\textit {dd}}$ for low power consumption worsen the reliability issue. In order to suppress the stressing current, special pixel signal designs with larger transition time are shown effective.

A simulation study of the influence of a high-k insulator and source stack on the performance of a double-gate tunnel FET

The influence of incorporating HfO2 as a dielectric at the drain side and a silicon stack at the source side on the electrical performance of a double-gate tunnel field-effect transistor (TFET) is investigated by comparing a conventional TFET structure with four other structures in which the gate dielectric material is either homogeneous or heterogeneous while the insulator on the drain side is either SiO2 or HfO2. Moreover, a structure with a silicon source stack is proposed and the figures of merit of the resulting device are compared with other counterparts. The results of the simulations reveal that the presence of an HfO2 insulator on the drain side reduces the ambipolar conduction while the heterogeneous gate dielectric enhances the drive current and transconductance. However, the use of HfO2 slightly deteriorates the source–gate and drain–gate capacitances in comparison with the conventional TFET. Furthermore, the incorporation of a silicon source stack along with a heterogeneous gate dielectric and HfO2 insulator on the drain side leads to a higher ION/IOFF ratio, lower subthreshold slope (S), and lower ambipolar conduction in the studied TFET with channel length of 50 nm.

Modeling Avalanche Induced Degradation for 4H-SiC Power MOSFETs

In this letter, a model that predicates the degradation of 4H-SiC power metal-oxide-semiconductor field-effect transistors under repetitive avalanche stress is proposed. Since positive charges are injected into the gate oxide interface of the JFET region, the gate-drain capacitance $(C_{gd})$ is chosen as the targeted parameter to quantify the avalanche induced degradation. The relationship between the increment of the $C_{gd}$ and the injected charge density is calculated and validated to demonstrate the rationale of the model. It is found that the increment of $C_{gd}$ has a linear relationship with the logarithm of the total avalanche energy ( E AV) dissipated on the device. Excellent agreement is also achieved between the simulated degraded data and the measured one, further proving the accuracy of the proposed degradation model.

Design of a Digital Tool for Communication and Analysis of Air Quality in Tabasco, Mexico.

In this paper, for the first time, an analytical stability model for quantum square-shaped extended source P-N-P-N tunneling field-effect transistor (P-N-P-N TFET) with silicon carbide substrate is developed that includes the effects of gate-source capacitance, gate-drain capacitance, effective gate resistance, time constant and transconductance. A nonquasistatic RF small-signal model has been used and stability that was extracted from analytical equations of its Y-parameters. The obtained analytical expression for stability is compared with device simulation results and excellent agreement is found up to 100 GHz. The stability performance of a quantum square-shaped extended source P-N-P-N TFET with silicon carbide substrate is also studied analytically considering pocket width and doping variation. The results strongly confirm that the proposed model is accurate and suitable for the quantum square-shaped extended source P-N-P-N TFET in the high-frequency regime.

TCAD Simulation of the Doping-Less TFET with Ge/SiGe/Si Hetero-Junction and Hetero-Gate Dielectric for the Enhancement of Device Performance

The device structure of DLTFET is optimized by the Silvaco TCAD software to solve the problems of lower on-state current and larger miller capacitance of traditional doping-less tunneling field effect transistors (DLTFETs), and the performance can be greatly improved. Different from the traditional DLTFETs, the source region and pocket region of the doping-less TFET with the Ge/SiGe/Si hetero-junction and hetero-gate dielectric (H-DLTFET), respectively, use the narrow band-gap semiconductor Ge and SiGe materials, and the channel and drain region both use the silicon material. The H-DLTFET device use the Ge/SiGe hetero-junction engineering to decrease the tunneling barrier width, increase the band-to-band tunneling current, and obtain the higher current switching ratio and ultra-low sub-threshold swing (SS). Besides, the gate dielectric under auxiliary gate uses the low-k dielectric SiO2 material, which can effectively reduce the miller capacitance and improve the capacitance and frequency characteristics. The on-state current, switching ratio, trans-conductance, output current, and output conductance values of H-DLTFET can be increased by two, two, one, one, and one order of magnitude when compared with the DLTFET, respectively. Meanwhile, the point SS and average SS, respectively, decrease from 13 mV/Dec and 31.6 mV/Dec to 5 mV/Dec and 14.3 mV/Dec, and the gate-drain capacitance decrease from 0.99 fF/μm to 0.1 fF/μm. Besides, the cutoff frequency and gain bandwidth product of H-DLTFET are much larger than that of DLTFET, which can be explained by the excellent DC characteristics. The above simulation results show that the H-DLTFET has the better frequency characteristics, so it is more suitable for applications of ultra-low-power integrated circuits.

Effect of electron radiation on small-signal parameters of NMOS devices at mm-wave frequencies

The effect of electron radiation on the forward-active small-signal model parameters for 0.35 μm CMOS devices is reported. Four devices with different gate widths were exposed to electron radiation using a Strontium 90 (Sr 90) radiation source at dose rates of 200 kRad (Si)/hr up to a total radiation dose of 2.7 MRad. S-parameters were measured, and small-signal models extracted, both pre-irradiation and at regular dose intervals. Relationships between small-signal model parameters and total radiation dose d were derived and used to calculate small-signal parameters. The major model variations due to total ionizing dose exposure were increases in the gate resistance (Rg), gate drain capacitance (Cgd) and gate source capacitance (Cgs), with a reduction in transconductances (gm and gds). This results in S11 and S22 becoming more resistive as d is increased, with a decrease in the unilateral gain, fT and fmax. The application of the data in predictive modelling of radiation damage is demonstrated.

Degradation mechanisms of InP-based high-electron-mobility transistors under 1 MeV electron irradiation

In this paper, InP-based high electron mobility transistors were investigated for an electron fluence of 5 × 1015 cm−2 at 1 MeV. The channel current and transconductance were reduced by 7.8% and 12.6% after electron irradiation. Meanwhile, the ION/IOFF ratio was reduced from 2.47 × 1012 to 2.16 × 102 and the SS was increased from 116.8 m mV dec−1 to 125.9 mV dec−1 after electron irradiation. To understand the degeneration behavior, the carrier concentration and mobility were calculated by the charge control model. Unlike, previous studies on the degradation behavior upon irradiation, the results show that these changes could only be attributed to the reduction of mobility in the channel by the irradiation-induced defects. The AFM and pulsed I–V curves measurement results proved that the Coulomb scatter effect was increased after electron irradiation, which led to decrease the carrier mobility. Besides, the current gain cut-off frequency (f T) was reduced from 139.4 GHz to 125.5 GHz and maximum oscillation frequency (f max) was reduced from 226.2 GHz to 206.1 GHz after electron irradiation. The degradation of frequency properties was mainly due to the increase of gate-drain capacitance and the channel resistance.

In₀.₅₃Ga₀.₄₇As/InAs Composite Channel MOS-HEMT Exhibiting 511 GHz fτ and 256 GHz f max

An In 0.53 Ga 0.47 As/InAs composite channel MOS-HEMT exhibiting peak $f_{\tau } = 511$ GHz and peak ${f} _{\max }= 285$ GHz is demonstrated. Additionally, another device exhibiting peak $f_{\tau } = 286$ GHz and peak ${f} _{\max }= 460$ GHz is reported. The devices have a 1 nm / 3 nm Al x O y N z interfacial layer and ZrO 2 gate dielectric on a 2 nm / 4 nm In 0.53 Ga 0.47 As / InAs composite channel with a modulation doped In 0.52 Al 0.48 As back barrier. To reduce parasitic gate-source and gate-drain capacitances, a modulation doped In 0.52 Al 0.48 As / In 0.53 Ga 0.47 As / InAs composite quantum well is included between the gate edges and the N+ source and drain. Compared to the work of Wu et al. , addition of an In 0.52 Al 0.48 As back-barrier, scaling of S/D metal spacing, and scaling of channel thickness has enabled improved transconductance and increased ${f} _{\tau }$ . Short gate length devices ${f} _{\max }$ are limit by high $R_{G}$ due to poor metal filling of the T-Gate stem and large $C_{DS}$ due to a conductive etch stop layer. Long gate length devices exhibit better metal filling, reduced $R_{G}$ , and balanced ${f} _{\tau }$ , ${f} _{\max }$ . Devices exhibit 10–15% DC-1 GHz $g_{m,e}$ suggesting that the high-k / semiconductor interface has low $D_{it}$ .

An insight to the performance of vertical super-thin body (VSTB) FET in presence of interface traps and corresponding noise and RF characteristics

We investigated vertical super-thin body (VSTB) FET performance in presence of different interface (HfO2/Si) trap distributions (uniform and Gaussian) and concentrations using TCAD tools. For trap concentration (TC) of 1013 eV−1 cm−2, the percentage change in on-to-off current ratio (Ion/Ioff) is 93.91% for uniform trap (UT) and 49.8% for Gaussian trap (GT) distribution. For the same TC, subthreshold swing (SS) shows percentage change of 5.1% for UT and 11.41% for GT distribution. Thus, the device performance shows good immunity for TC up to 1013 eV−1 cm−2. However, for TC = 1014 eV−1 cm−2 SS degrades significantly. The influence of traps on the cumulative effect of three noise sources (diffusion + generation–recombination/G–R + flicker) and on individual noise sources (G–R and diffusion) is explained qualitatively at low and high frequencies (f = 1 MHz and 10 GHz). The study shows that the overall noise cannot disturb the device performance at very high frequency. Various radio-frequency (RF) parameters like transconductance (gm), total input capacitance (Cgg), gate-drain capacitance (Cgd), unit-gain cutoff frequency (fT), and gain–bandwidth-product (GBP) are also studied for variation of trap types. For TC = 1014 eV−1 cm−2, the percentage change in fTmax (GBPmax) is − 21.43% (− 8%) for UT and − 22.86% (− 9.6%) for GT distribution.

An Assessment of Step Patterned Gate Oxide Superjunction Trench MOSFET for Potential Benefits

A 600 V-class step patterned gate oxide trench (SPGOT) superjunction vertical device incorporating gate engineering is proposed in this paper. An $$n^{+}$$ polysilicon gate is segregated into three steps of varied length and oxide thickness. To improve the device performance, the gate oxide in the SPGOT structure is narrow towards the source and wide towards the drain. This modification increases the gate–source capacitance, indicating higher transconductance, and reduces gate–drain capacitance, suggesting lower switching delay. The gate length is optimized to achieve enhanced performance indicators. Electrical performance is investigated and analyzed using 2-D numerical simulations. The optimized results reveal 9.7% and 26.14% reduction in specific resistance ( $$R_{\rm on} {\cdot} A$$ ) and gate–drain charge ( $$Q_{\rm GD}\cdot A$$ ), respectively, without any reduction in breakdown voltage. The engineered gate structure further exhibits a 43% and a 33.2% improvement in switching delay and figure of merit ( $$R_{\rm on}\cdot A$$ × $$Q_{\rm GD}\cdot A$$ ), respectively, over a conventional device.

Impact of Gate–Source Overlap on the Device/Circuit Analog Performance of Line TFETs

The gate–source overlap length ( ${L}_{{\text {OV}}}$ ) in the line tunneling FET (L-TFET) can be used as a design parameter to improve the analog circuit performance. In this paper, we investigate the drain current ( ${I}_{D}$ ) dependence on ${L}_{{\text {OV}}}$ , considering the electrostatics of the gate–source overlap region. It is observed that ${I}_{D}$ increases with ${L}_{{\text {OV}}}$ exhibiting a nonlinear behavior. This happens as the impact of the lateral electric field at the far end of the tunnel junction reduces, thereby reducing the tunneling rate. Based on our semiempirical physical ${I}_{D}$ – ${L}_{{\text {OV}}}$ model, a novel ${L}_{{\text {OV}}}$ variation-aware small signal model for L-TFET is also proposed. The output resistance and the gate–drain capacitance remain almost independent of ${L}_{{\text {OV}}}$ in the saturation regime. The gate–source capacitance and the transconductance linearly increase with ${L}_{{\text {OV}}}$ . A common source amplifier is demonstrated with ~2.4 times increase in the voltage gain when ${L}_{{\text {OV}}}$ is increased from 20 to 50 nm, with a penalty of ~10% in the bandwidth. We observe that it is not possible to achieve the gain similar to one obtained using 2.5 times increase in ${L}_{{\text {OV}}}$ even after increasing the device width five times. However, the bandwidth reduces 30% at such width owing to an increase in the gate capacitances.

Modelisation and Simulation of Cgs.op and Cgd.op Capacities of GaAs MESFETs OPFET

An analytical of new theoretical model has been developed to study the Capacitance characteristics for an optically controlled Gallium Arsenic Metal Semiconductor Field Effect Transistor MESFET (OPFET) doped uniformly. The model takes the effects of photoconductive and photovoltaic into account that determine the device characteristics in the illuminated condition. It has been presented here for an analysis of extrinsic and intrinsic parameters such as, gate capacitances including both of the gate-source capacitances gate-drain capacitances under dark and illumination condition. The numerical results have also been compared with the reported data experience in the literature and a good agreement is observed.

Workfunction engineered stepped gate SJ UMOS with reduced specific resistance for high speed applications

In this paper, trench superjunction MOS (SJ UMOS) utilizing workfunction engineered stepped gate for performance enhancement is proposed. N+ polysilicon (Φm = 4.17 eV) layer in between two P+ polysilicon (Φm = 5.25 eV) layer connected by a metal gate is incorporated in the proposed device. Additionally, gate oxide thickness is increased in steps from source to drain resulting in enhanced gate-source capacitance and reduced gate-drain capacitance. The electrical behavior of conventional and proposed device is investigated using 2D numerical simulations. The results indicate 19.5% reduction in specific resistance without degrading the breakdown voltage. Further, the proposed structure also exhibits 28.9% reduction in specific gate to drain charge, 30.5% increment in gate to source charge and 54% reduction in switching delay. In addition to this, Baliga’s figure of merit (BFOM) along with other technology figure of merit (FOM) has also been evaluated, demonstrating a 26% increment in BFOM. The significant improvement in FOM is attributed to reduced specific resistance and gate to drain charge of the proposed structure. Additionally, the impact of temperature on device performance is also evaluated and no degradation in the device parameters is observed.