Workfunction engineered stepped gate SJ UMOS with reduced specific resistance for high speed applications

Abstract

In this paper, trench superjunction MOS (SJ UMOS) utilizing workfunction engineered stepped gate for performance enhancement is proposed. N+ polysilicon (Φm = 4.17 eV) layer in between two P+ polysilicon (Φm = 5.25 eV) layer connected by a metal gate is incorporated in the proposed device. Additionally, gate oxide thickness is increased in steps from source to drain resulting in enhanced gate-source capacitance and reduced gate-drain capacitance. The electrical behavior of conventional and proposed device is investigated using 2D numerical simulations. The results indicate 19.5% reduction in specific resistance without degrading the breakdown voltage. Further, the proposed structure also exhibits 28.9% reduction in specific gate to drain charge, 30.5% increment in gate to source charge and 54% reduction in switching delay. In addition to this, Baliga’s figure of merit (BFOM) along with other technology figure of merit (FOM) has also been evaluated, demonstrating a 26% increment in BFOM. The significant improvement in FOM is attributed to reduced specific resistance and gate to drain charge of the proposed structure. Additionally, the impact of temperature on device performance is also evaluated and no degradation in the device parameters is observed.