An Assessment of Step Patterned Gate Oxide Superjunction Trench MOSFET for Potential Benefits

Abstract

A 600 V-class step patterned gate oxide trench (SPGOT) superjunction vertical device incorporating gate engineering is proposed in this paper. An $$n^{+}$$ polysilicon gate is segregated into three steps of varied length and oxide thickness. To improve the device performance, the gate oxide in the SPGOT structure is narrow towards the source and wide towards the drain. This modification increases the gate–source capacitance, indicating higher transconductance, and reduces gate–drain capacitance, suggesting lower switching delay. The gate length is optimized to achieve enhanced performance indicators. Electrical performance is investigated and analyzed using 2-D numerical simulations. The optimized results reveal 9.7% and 26.14% reduction in specific resistance ( $$R_{\rm on} {\cdot} A$$ ) and gate–drain charge ( $$Q_{\rm GD}\cdot A$$ ), respectively, without any reduction in breakdown voltage. The engineered gate structure further exhibits a 43% and a 33.2% improvement in switching delay and figure of merit ( $$R_{\rm on}\cdot A$$ × $$Q_{\rm GD}\cdot A$$ ), respectively, over a conventional device.