Gate-drain Capacitance Research Articles

Improving dynamic performance for split-gate trench power MOSFETs using variable vertical doping profile

In this paper, a split-gate trench power MOSFET (SGT) with a variable vertical doped (VVD) drift region is proposed. The VVD SGT MOSFET features ultra-low gate-drain charge (QGD) and low switching losses. Due to the introduction of variable vertical doping, the concentration of the drift region near the source is relatively low. The depletion layer outside the trench of the new structure widens towards the drain during depletion spreading, effectively reducing the depletion layer capacitance and thus greatly reducing the gate-drain capacitance (CGD). The significant reduction of QGD and total switching losses is confirmed by simulation. Compared with the conventional split-gate trench MOSFET, the dynamic figure of merit RON × QGD = 22.60 mΩ nC and turn-off loss of the proposed VVD SGT MOSFET are reduced by 42% and 37%, respectively. Moreover, the proposed structure also demonstrates an improvement in the reverse recovery performance.

TCAD-Based Investigation of a 650 V 4H-SiC Trench MOSFET with a Hetero-Junction Body Diode.

In this paper, a 650 V 4H-SiC trench Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) with a hetero-junction diode (HJD) and double current spreading layers (CSLs) is proposed and studied based on Sentaurus TCAD simulation. The HJD suppresses the turn-on of the parasitic body diode and improves the performance in the third quadrant. CSLs with different doping concentrations help to lower the on-state resistance as well as the gate-drain capacitance. As a result, the on-state resistance is decreased by 47.82% while the breakdown voltage remains the same and the turn-on and turn-off losses of the proposed structure are reduced by 83.39% and 68.18% respectively, compared to the conventional structure.

A New Gate Driver for Suppressing Crosstalk of SiC MOSFET

High switching-speed Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistor (SiC MOSFET) has serious crosstalk issues. During the turn-ON transition and turn-OFF transition of the active switch in a phase-leg configuration, the voltage drops across the common-source inductor and the displacement current of the gate-drain capacitor of the OFF-state switch induce a spurious pulse on its gate-source voltage. This paper proposes a new gate driver using two Bipolar Junction Transistors (BJTs) and one diode to connect the gate terminal of SiC MOSFET and the negative driver voltage, which provides a low impedance path to bypass the displacement current of the gate-drain capacitor when crosstalk issues occur. The simulation results prove the proposed driver is valid on suppressing the crosstalk issue. The comparisons between the prior drivers and the proposed driver show the superiority of the proposed driver. Finally, the proposed gate driver is successfully implemented and experimentally verified on a 1.1 kW synchronous buck prototype.

High Performance 3.3 kV SiC MOSFET Structure with Built-In MOS-Channel Diode

Built-in freewheeling diode metal–oxide–semiconductor field-effect transistors (MOSFETs) that ensure high performance and reliability at high voltages are crucial for chip integration. In this study, a 4H–SiC built-in MOS-channel diode MOSFET with a center P+ implanted structure (CIMCD–MOSFET) is proposed and simulated via technology computer-aided design (TCAD). The CIMCD–MOSFET contains a P+ center implant region, which protects the gate oxide edge from high electric field crowding. Moreover, the region also makes it possible to increase the junction FET (JFET) and N-drift doping concentration of the device by dispersing the high electric field. Consequently, the CIMCD–MOSFET is stable even at a high voltage of 3.3 kV without static degradation and gate oxide reliability issues. The CIMCD–MOSFET also has higher short-circuit withstanding capability owing to the low saturation current and improved switching characteristics due to the low gate-drain capacitance, compared to the conventional MOSFET (C–DMOSFET) and the built-in Schottky barrier diode MOSFET (SBD–MOSFET). The total switching time of a CIMCD–MOSFET is reduced by 52.2% and 42.2%, and the total switching loss is reduced by 67.8% and 41.8%, respectively, compared to the C–DMOSFET and SBD–MOSFET.

A novel optimum variation lateral doping SiC lateral double-diffused metal oxide semiconductor with improved performance

In thsi paper a novel optimum variation lateral doping 4H-SiC lateral double-diffused metal oxide semiconductor (LDMOS) field-effect transistor with improved performance is proposed and numerically simulated. For the proposed 4H-SiC LDMOS, an optimized three-stage variation of lateral doping (VLD) p-top layer is employed in the drift region; thus the doping concentration of the n-drift region can be significantly increased, resulting an ultra-low specific resistance (R on,sp). The breakdown voltage (BV) is also improved, since the electric field distribution of the drift region is optimized. The current saturation characteristic, gate–drain capacitance (C GD) and gate-to-drain charge (Q gd) of the proposed device are all improved, thanks to the effect of the source-connected p-top region. Compared with a conventional LDMOS, the numerical simulation results show that the BV, R on,sp and Q gd of the proposed LDMOS are improved by more than 11.9%, 47.3% and 46.3%, respectively. The three-dimensional simulation result indicates that the entire three-stage p-top VLD layer can be produced by one-time fabrication process, which brings great convenience to future production.

Entangled microwave photons generation using cryogenic low noise amplifier (transistor nonlinearity effects)

This article mainly focuses on important quantum phenomenon called entanglement arising the nonlinearity property. This study uses a unique approach in which transistor nonlinearity effect (third-order nonlinearity) entangled microwave photons are created in a cryogenic low-noise amplifier (LNA). For entanglement analysis, the Hamiltonian of the designed cryogenic LNA (containing two coupled oscillators) is derived, and then, using the dynamic equation of motion, the oscillator’s number of photons and the phase-sensitive cross-correlation factor are calculated in the Fourier domain to calculate the entanglement metric. The oscillators are coupled to each other through the gate–drain capacitor, and nonlinear transconductance is as an important factor strongly manipulating the entanglement. As a main conclusion, the study shows that the designed circuit using transistor third-order nonlinearity has the ability to generate the entangled microwave photons at very low intrinsic transconductance and more importantly when the noise figure (NF) is strongly minimized. As a complementary task, the printed circuit board of the cryogenic LNA is designed and simulated to verify the ability of the circuit to achieve an ultralow NF, by which the probability of the generation of entangled microwave photons is increased.

Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs.

650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal layout was used for the 650 V SiC MOSFETs to reduce the ON-resistance. The devices were packaged into open-cavity TO-247 packages for evaluation. Trade-off analysis of the static and dynamic performance of the 650 V SiC power MOSFETs was conducted. The measurement results show that a short JFET region with an enhanced JFET doping concentration reduces specific ON-resistance () and lowers the gate-drain capacitance (). It was experimentally shown that a thinner gate oxide further reduces , although with a penalty in terms of increased . A design with 0.5 m half JFET width, enhanced JFET doping concentration of cm−3, and thin gate oxide produces an excellent high-frequency figure of merit (HF-FOM) among recently published studies on 650 V SiC devices.

Analysis and design of a 55–74 GHz ultra‐compact low‐noise amplifier using highly asymmetric transformers

This letter presents a low-noise amplifier with a 3 dB-bandwidth, from 55 to 74 GHz, excellent noise performance and low power consumption based on a three-stage common-source topology. For the first time to the authors' best knowledge, an analytical equation that also considers the gate–drain capacitance is derived for the employed shunt–series transformer feedback input matching network. To enable shunt–series transformer feedback matching without significant gain reduction a highly asymmetric transformer is designed. Furthermore, a compact transformer-implemented T-shaped output matching network is investigated to minimize the required area. To prove these concepts, the circuit has been fabricated in a 22 nm fully depleted silicon-on-insulator technology. Thanks to the transformer-based matching, an ultra-compact active footprint of 0.039 mm2 is achieved. At a power consumption of 8.4 mW from a 0.41 V supply an average noise figure of 4.8 dB and a peak gain of 14.2 dB has been measured. In- and output matching better than −10 dB over the 19 GHz wide 3 dB-bandwidth are demonstrated.

Diminish Short Channel Effects on Cylindrical GAA Hetero-gate Dielectric TFET using High-Density Delta

The examined work elucidates a novel concept on Gate All Around (GAA) hetero dielectric gate-cylindrical tunnel field-effect transistor (TFET) to reduce SCEs. In this paper, a hetero dielectric gate (HeG) integrated with Silicon-Germanium (Si-Ge) substrate material is proposed along with a novel placement of a high-density delta (HDD) layer across the source–channel junction to achieve high ION of 1.12 × 10−4 A/µm and robust IOFF of 9.7 × 10−17 A/µm at Vgs = 1.2 V with steepest subthreshold swing (SS) of 55 mV/decade. Designing and computation of the proffered structure have been done with the computer-aided design (TCAD) 3D device computation software. The systematic investigation in terms of AC and DC parameters, such as ON-current, OFF-current, Miller Capacitances (Gate-Drain Capacitance (Cgd)) and Gate-Source Capacitance (Cgs), are examined. Hetero-gate dielectric Cyl-TFET with high-density delta (HDD) is superior to other conventional structures. The result outcomes included a trap analysis while incorporating the hot charge carriers inside the oxide for improved device reliability. Furthermore, a low Cgd of 58fF and high Cgs of 6.6fF at Vds = 0.3 V have been achieved.

Evidence of Hot-Hole Induced Degradation in Lateral NDRIFT MOSFET: Characterization and TCAD Analysis

The role of secondary hot holes in the degradation of n-channel lateral drift MOSFETs, possibly leading to gate oxide breakdown, is discussed. Trapping of positive charges in the gate and field oxides and the formation of interface states under hot-carrier stress (HCS) have been successfully monitored by means of direct current current-voltage (DCIV) measurements and through gate-drain capacitance measurements. Experimental data have been complemented with Technology Computer Aided Design (TCAD) analysis. A degradation model including both hot-electrons and secondary hot-holes induced degradation capable of interpreting and reproducing measured data is proposed. Simulations allow to gain insights in the kinetics laws governing charge trapping and interface states generation along the silicon/oxide interface. The drift kinetics of the ON-state resistance have been also characterized and reproduced by simulations.

A 90 GHz Broadband Balanced 8-Way Power Amplifier for High Precision FMCW Radar Sensors in 65-nm CMOS.

We present a W-band 8-way wideband power amplifier (PA) for a high precision frequency modulated continuous wave (FMCW) radar in 65-nm CMOS technology. To achieve a broadband operation with an improved output power for a high range resolution and high distance coverage of FMCW radar sensors, a balanced architecture is employed with the Lange coupler which naturally combines the output powers from two 4-way push-pull PAs. By utilizing a transformer-based push-pull structure with a cross-coupled capacitive neutralization technique, the gate-drain capacitance of the 4-way PA is compensated for the stabilization with an improved power gain. Interstage matching was performed with transformers for a reduced loss from the matching network and minimal area occupation. The implemented balanced 8-way PA achieved a saturated output power (Psat) of 16.5 dBm, a 1-dB compressed output power (OP1dB) of 13.3 dBm, a power-added efficiency (PAE) of 9.9% at 90 GHz and 3-dB power bandwidth was 20.4 GHz (79.2–99.6 GHz).

Silicon and Germanium Vertical Super-Thin Body (VSTB) FET: A Comparative Performance Overview Including Architectural Stress-Strain Impact

This article aims to develop a comprehensive understanding of the comparative performance of a vertical super-thin body (VSTB) FET in terms of two device material variations (silicon/Si and germanium/Ge) first time with the aid of 3D Senaturus TCAD tool. More importantly, the influence of the inevitable architectural stress (exerted over the thin body by the thick dielectric walls) on the transfer characteristic of the device is also addressed for Si/Ge device. From the perspective of suitability in high-performance circuits, Ge outperforms Si by enhancing on-state current (I on ) by 30.28, 30.29, 29.91, and 26.98 μA at channel length of 10, 20, 30, and 40 nm, respectively, with an improvable deterioration in off-state leakage current, subthreshold swing, and drain-induced-barrier-lowering. Further, a three-dimensional stress analysis reveals that stress increases I on more in Ge-device compared to its Si-counterpart. As expected, a similar nature is observed for the strain application. Finally, the radio-frequency study shows that although the relative performance of Ge with respect to Si in terms of input capacitance, gate-drain capacitance, and output conductance is inferior, the greater transconductance of Ge than Si lowers intrinsic delay and enhances the peaks of intrinsic gain, unit-gain cut-off frequency, and gain-bandwidth-product.

The Influence of Repetitive UIS on Electrical Properties of Advanced Automotive Power Transistors

This paper investigates a degradation of three types of automotive power MOSFETs through repetitive Unclamped Inductive Switching (UIS) test typically used to evaluate the avalanche robustness of power devices. It is not uncommon in switching applications that greater than the planned voltage for voltage spikes can occur, so even the best electronic designs may encounter frequent avalanche events. Hence, there is a need to analyse the impact of repetitive avalanching on the electrical performance of power transistors. This article focused on the shift of main electrical parameters: on-resistance R_{ON}, breakdown voltage V_{BR}, threshold voltage V_{TH}, and corresponding characteristics, as well as capacitances. Analysis proved that DMOS transistors are less vulnerable to repetitive avalanching. The most impacted parameter was on-resistance R_{DSon}, where a 14 % increase was observed after 6 x 10^7 stress pulses. The parameters shift is attributed to hot carrier injection in the space charge region of blocking PN junction and involves mainly defects generation/activation in the drain side region of the gate oxide. For the TrenchMOS transistor, a significant shift of I-V curves was observed with considerable impact on the R_{ON} where an increase of 22 % was observed. The trench corner is verified to be the mainly degraded region by Synopsys Technology Computer Aided Design (TCAD) simulations. Degradation of drain-gate capacitance C_{DG} and input capacitance C_{in} was observed in all three types of analysed structures. DLTS was used to verify the generation/activation of defects invoked by stress. An increase of DLTS signal corresponding to energy levels of oxygen vacancies and impurities in SiO_2 and on interfaces were detected on stressed samples.

Применение нейронных сетей при построении нелинейных моделей полевых транзисторов

The nonlinear model of a field-effect transistor based on the mathematical apparatus of the theory of artificial neural networks was developed. The main feature of this model is the possibility of training neural networks used to approximate the current-voltage characteristic and the gate-drain and gate-source capacitances of a nonlinear transistor model by using optimization algorithms built into popular microwave CAD systems. This makes it possible to use the well-known advantages of neural networks in the problems of function approximation to increase the reliability of the results of non-linear modeling of microwave devices based on field-effect transistors.

The effect of nonideal boundary condition on instability of THz plasma waves in quantum field-effect transistors

The instability of THz plasma waves propagating along a channel of field-effect transistors opens up a new mechanism of emission of THz waves. In this work, we investigate the instability of THz plasma waves in field-effect transistors in the presence of quantum effects and nonideal boundary condition at the source and the drain by using the quantum hydrodynamic model. The results show that the THz plasma waves will be unstable when the gate–source capacitances are larger than gate–drain capacitances and the instability increment can be increased by increasing gate–source capacitances or decreasing gate–drain capacitances. The results of this work give nano-field-effect transistors an advantage in achieving real THz oscillations.

Instability of parasitic capacitance in T-shape-gate enhancement-mode AlGaN/GaN MIS-HEMTs

Parasitic capacitances associated with overhangs of the T-shape-gate enhancement-mode (E-mode) GaN-based power device, were investigated by frequency/voltage-dependent capacitance–voltage and inductive-load switching measurements. The overhang capacitances induce a pinch-off voltage distinguished from that of the E-mode channel capacitance in the gate capacitance and the gate–drain capacitance characteristic curves. Frequency- and voltage-dependent tests confirm the instability caused by the trapping of interface/bulk states in the LPCVD-SiN x passivation dielectric. Circuit-level double pulse measurement also reveals its impact on switching transition for power switching applications.

Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example.

The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (Cgd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (Eox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the Cgd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (Vth) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations.

Modeling and Suppression of the Crosstalk Issue Considering the Influence of the Parasitic Parameters of SiC MOSFETs

Due to the extremely fast switching speed of the SiC MOSFET, its crosstalk issue is more serious than that of the Si IGBT. Therefore, in order to ensure the reliability of the SiC MOSFET converters, the crosstalk problem must be solved firstly. Most of the existing crosstalk suppression methods are aimed at decreasing the crosstalk voltage introduced by the parasitic gate-drain capacitance (Miller capacitance), ignoring the influence of other parasitic parameters on the crosstalk voltage, such as the common source inductance, which may also lead to more serious reliability problems. Thus, this paper firstly establishes the mathematical model of the switching process of the SiC MOSFET half-bridge inverter. Then, the effects of various parasitic parameters (the gate-source capacitance, the gate-drain capacitance, the common source inductance, the gate inductance, the drain inductance) on the crosstalk voltage are analyzed and modeled in detail, which is verified by experiments. Based on the analyses and models, a novel crosstalk voltage suppression circuit is proposed, which can not only suppress the crosstalk caused by the gate-drain capacitance, but also solve the crosstalk issue considering the influence of other parasitic parameters, such as the common source inductance. Finally, a double pulse test platform is established to verify the effectiveness of the designed crosstalk suppression circuit under different voltage/current conditions.

Impact of gate offset in gate recess on DC and RF performance of InAlAs/InGaAs InP-based HEMTs

A set of 100-nm gate-length InP-based high electron mobility transistors (HEMTs) were designed and fabricated with different gate offsets in gate recess. A novel technology was proposed for independent definition of gate recess and T-shaped gate by electron beam lithography. DC and RF measurement was conducted. With the gate offset varying from drain side to source side, the maximum drain current (I ds,max) and transconductance (g m,max) increased. In the meantime, f T decreased while f max increased, and the highest f max of 1096 GHz was obtained. It can be explained by the increase of gate–source capacitance and the decrease of gate–drain capacitance and source resistance. Output conductance was also suppressed by gate offset toward source side. This provides simple and flexible device parameter selection for HEMTs of different usages.

Analysis of nanoscale digital circuits using novel drain-gate underlap DMG hetero-dielectric TFET

In this paper, the investigation of dual metal double gate (DMG) hetero-dielectric TFET with drain-gate underlap for nanoscale digital applications is analyzed. Drain-gate underlap TFET is used to achieve lower ambipolar current (Iambi) and low leakage current (Ioff) than a conventional hetero-dielectric TFET. The performance analysis has been done in terms of bias dependent parasitic capacitances. Results reveal that drain-gate underlap suppresses the gate-drain capacitance by 5.6% than the conventional DMG TFET which in turn has a positive effect on the digital applications. The prime performance metrics such as rising/falling delay, propagation delay and peak overshoot voltages are analyzed for drain-gate underlap DMDG TFET inverter. The propagation delay and the overshoot voltage show significant decrease of 9.27% and 1.24% respectively for the drain-gate underlapped TFET for a supply voltage (Vdd) of 0.5V. Thus the drain-gate underlap TFET is considered to be a good candidate for nanoscale digital applications.