Gate Current Density Research Articles

Threshold voltage instability by charge trapping effects in the gate region of p-GaN HEMTs

In this work, threshold voltage instability of normally off p-GaN high electron mobility transistors has been investigated by monitoring the gate current density during a device on-state. The origin of gate current variations under stress has been ascribed to charge trapping occurring at different interfaces in the metal/p-GaN/AlGaN/GaN system. In particular, depending on the stress bias level, electrons (VG < 6 V) or holes (VG > 6 V) are trapped, causing a positive or negative threshold voltage shift ΔVTH, respectively. By monitoring the gate current variations at different temperatures, activation energies associated with the electrons and holes trapping could be determined and correlated with the presence of nitrogen (electron traps) or gallium (hole traps) vacancies. Moreover, the electrical measurements suggested the generation of a new electron-trap upon long-time bias stress, associated with the creation of crystallographic dislocation-like defects extending across different interfaces (p-GaN/AlGaN/GaN) of the gate stack.

Large Area Emission in p-Type Polymer-Based Light-Emitting Field-Effect Transistors by Incorporating Charge Injection Interlayers.

Organic light-emitting field-effect transistors (LEFETs) provide the possibility of simplifying the display pixilation design as they integrate the drive-transistor and the light emission in a single architecture. However, in p-type LEFETs, simultaneously achieving higher external quantum efficiency (EQE) at higher brightness, larger and stable emission area, and high switching speed are the limiting factors for to realise their applications. Herein, we present a p-type polymer heterostructure-based LEFET architecture with electron and hole injection interlayers to improve the charge injection into the light-emitting layer, which leads to better recombination. This device structure provides access to hole mobility of ~2.1 cm2 V−1 s−1 and EQE of 1.6% at a luminance of 2600 cd m−2. Most importantly, we observed a large area emission under the entire drain electrode, which was spatially stable (emission area is not dependent on the gate voltage and current density). These results show an important advancement in polymer-based LEFET technology toward realizing new digital display applications.

Batch-Fabricated WSe₂-on-Sapphire Field-Effect Transistors Grown by Chemical Vapor Deposition

Stepper-based batch fabrication of top-gated field-effect transistors (FETs) is demonstrated on few-layer WSe2-on-sapphire grown by chemical vapor deposition. This article reports the electrical characterization of 94 transistors with three different transistor structures. ON-/ OFF-current ratios exceeding 105 at room temperature with noise-floor-limited gate current and contact-limited ON-current density of 15 nA/ $\mu \text{m}$ was achieved for FETs using a structure in which the gate overlaps the source and drain contacts. Two transistors with open channel access regions are used to allow ion doping through polyethylene oxide: cesium perchlorate (PEO: CsClO4) to induce electron and hole conductivity and allow characterization of the intrinsic FET characteristics. In these geometries, the ON-current increased by four orders of magnitude with ON-/ OFF-current ratio greater than 106 at ${V}_{\text {DS}} = -0.05$ V, compared to gate overlapped FETs. An analytic 2-D FET model was used to model the full current-voltage characteristics. This allowed the field-effect mobility to be extracted revealing the gate and drain field dependence for the first time. The fit of the measured characteristics from subthreshold to saturation is made with only four fitting parameters, revealing a field-dependent electron mobility ranging from 1 to 2.6 cm2/Vs.

Layer dependent direct tunneling behaviors through two dimensional titania nanosheets

Two dimensional titania nanosheets are drawing increasing attention in academic and industrial community because of their versatile properties. The elucidation of the electron tunneling effect through their intrinsic metal-oxide-metal (MOM) atomic structures is imperative to further advance their applications as atomic dielectrics and memristors. The direct tunneling behaviors through Ti1-δO24δ- nanosheets sandwiched by two metal electrodes are studied by a modified WKB approximation and conformed by ab-initio calculation. Our results show that the tunneling current density depends exponentially on the stack number of dielectric Ti1-δO24δ- layers, decreases by 3–4 orders of magnitude for each layer addition, varying from 106 to 10−8 A/cm2 in one- to five-layer MOM structures. Also, it is highlighted that the localized intercalation charges naturally embedded in chemically-derived Ti1-δO24δ- nanosheets could reduce tunneling current by 3 orders of magnitude and that a thickness threshold of three layers (∼2 nm) exists as to the titania nanosheets not to exceed a gate current density of 1 A/cm2 at 1 V. The present method could be extended to better clarify the electron tunneling behaviors in other two-dimensional gate dielectrics.

Influence of growth conditions of oxide on electrical properties of AlGaN/GaN metal–insulator–semiconductor transistors

AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) on a silicon substrate were fabricated with silicon oxide as a gate dielectric by sputtering deposition and electron-beam (EB) evaporation. It was found that the oxide deposition method and conditions have great influences on the electrical properties of HEMTs. The low sputtering temperature or oxygen introduction at higher temperature results in a positive equivalent charge density at the oxide/AlGaN interface (Nequ), which induces a negative shift of threshold voltage and an increase in both sheet electron density (ns) and drain current density (ID). Contrarily, EB deposition makes a negative Nequ, resulting in reduced ns and ID. Besides, the maximum transconductance (gm-max) decreases and the off-state gate current density (IG-off) increases for oxides at lower sputtering temperature compared with that at higher temperature, possibly due to a more serious sputter-induced damage and much larger Nequ at lower sputtering temperature. At high sputtering temperature, IG-off decreases by two orders of magnitude compared to that without oxygen, which indicates that oxygen introduction and partial pressure depression of argon decreases the sputter-induced damage significantly. IG-off for EB-evaporated samples is lower by orders of magnitude than that of sputtered ones, possibly attributed to the lower damage of EB evaporation to the barrier layer surface.

Mechanism of oxide thickness and temperature dependent current conduction in n+-polySi/SiO2/p-Si structures — a new analysis

The conduction mechanism of gate leakage current through thermally grown silicon dioxide (SiO2) films on (100) p-type silicon has been investigated in detail under negative bias on the degenerately doped n-type polysilicon (n+-polySi) gate. The analysis utilizes the measured gate current density JG at high oxide fields Eox in 5.4 to 12 nm thick SiO2 films between 25 and 300 °C. The leakage current measured up to 300 °C was due to Fowler–Nordheim (FN) tunneling of electrons from the accumulated n +-polySi gate in conjunction with Poole Frenkel (PF) emission of trapped-electrons from the electron traps located at energy levels ranging from 0.6 to 1.12 eV (depending on the oxide thickness) below the SiO2 conduction band (CB). It was observed that PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm and throughout the temperature range studied here. Understanding of the mechanism of leakage current conduction through SiO2 films plays a crucial role in simulation of time-dependent dielectric breakdown (TDDB) of metaloxide–semiconductor (MOS) devices and to precisely predict the normal operating field or applied gate voltage for lifetime projection of the MOS integrated circuits.

Breakdown Analysis of Magnetic Flip-Flop With 28-nm UTBB FDSOI Technology

Dielectric breakdown behaviors of high-performance nonvolatile magnetic flip-flop (NV-MFF) are investigated in this paper. Hybrid magnetic-CMOS flip-flop is implemented based on the spin torque transfer magnetic tunnel junction (MTJ) and 28-nm ultrathin body and buried oxide fully depleted silicon-on-insulator (FDSOI) technology. Transistor high- $\kappa$ metal-gate dielectric stacks and MTJ oxide barrier (MgO) are impacted by time-dependent oxide breakdown, which is shown by circuit-level characterizations: soft-breakdown as performance fluctuation/degradation and hard-breakdown as functional failure. We present the cumulative distribution of breakdown probability of both FDSOI CMOS transistors and MTJ devices. The traditional ohmic breakdown model is applied to evaluate circuit sensitivity to breakdown events. A quantitative analysis is performed considering the breakdown spots in the NV-MFF circuit. The increased gate current density $(\Delta I_{g}/WL)$ aggravates breakdown severity. Simulation results demonstrate both soft and hard breakdown behaviors in different building blocks, e.g., latency degradation in sense amplifier and output level degradation in other digital circuits. Results show that the oxide breakdown in the NV-MFF circuit is in accordance with the weakest link characteristic, as well as the area dependence.

Study of Hf-Ti-O Thin Film as High-k Gate Dielectric and Application for ETSOI MOSFETs

This work focused on the metal–oxide–semiconductor (MOS) capacitor and extremely thin silicon-on-insulator (ETSOI) p-type MOS field-effect transistor (pMOSFET) with laminated hafnium and titanium oxide (Hf-Ti-O) thin films as gate dielectric. The electrical behavior of the MOS capacitor shows that the capacitor with Hf-Ti-O gate dielectric has high performance with low equivalent oxide thickness (EOT, ~0.77 nm), small hysteresis (ΔVfb, ~4 mV), and gate current density of 0.33 A/cm2 at Vg = Vfb − 1 V. The dominant conduction mechanism of the Hf-Ti-O thin film (25°C to 125°C) was Schottky emission at lower gate voltage (−0.8 V to −0.2 V) and Fowler–Nordheim (F–N) tunneling at higher gate voltage (<−0.8 V). An ETSOI pMOSFET with 25 nm gate length (Lg) also exhibited good electrical properties with switch ratio of 3.2 × 104, appropriate threshold voltage of −0.16 V, maximum transconductance (Gmax) of 2.63 mS, drain-induced barrier lowering of 53 mV/V, and subthreshold swing of 65 mV/dec.

Study of the electrical and chemical properties of the multistep deposited and two-step (ultraviolet ozone cum rapid thermal) annealed HfO2 gate stack

The authors show that the TiN/HfO2/SiOx gate stack, formed via multistep deposition cum two-step anneal [comprising a room-temperature ultraviolet ozone (RTUVO) anneal and a subsequent rapid thermal anneal (RTA) at 420 °C], exhibits more superior electrical characteristics as compared to the gate stacks formed via multistep deposition cum single-step anneal (either RTUVO anneal or 420 °C RTA). The former exhibits more than an order of magnitude smaller gate current density, a 14-fold increase in the time-to-breakdown, and reduced positive oxide trapped charge as compared to the latter. The enhanced performance and reliability are attributed to the improved formation of Hf–O bonds in HfO2, resulting from the efficient incorporation of oxygen atoms facilitated by the thermal activation of the absorbed ozone. The findings provide insights into the improvement mechanism by the two-step anneal method for high-k last integration scheme.

Notice of Removal: A Novel Metal-Ferroelectric-Insulator-Silicon FET With Selectively Nucleated Lateral Crystallized Pb(Zr,Ti)O3 and ZrTiO4 Buffer for Long Retention and Good Fatigue

Removed.

Anomalous Width Dependence of Gate Current in High-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$K$ &lt;/tex-math&gt;&lt;/inline-formula&gt; Metal Gate nMOS Transistors

This letter analyzes the width dependence of gate current observed in nMOS transistors fabricated using the 28-nm gate-first CMOS process. It is experimentally shown that the gate current density is ~10× lower for 80-nm wide high permittivity (K) dielectrics and metal gate nMOS transistors compared with 1-μm wider ones. The physical mechanism responsible for this anomalous width dependence is identified and attributed to the reduction in the average number of positively charged oxygen vacancies present in HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> for narrow width transistors.

Electrically Tunable In-Plane Anisotropic Magnetoresistance in Topological Insulator BiSbTeSe2 Nanodevices

We report tunable in-plane anisotropic magnetoresistance (AMR) in nanodevices based on topological insulator BiSbTeSe2 (BSTS) nanoflakes by electric gating. The AMR can be changed continuously from negative to positive when the Fermi level is manipulated to cross the Dirac point by an applied gate electric field. We also discuss effects of the gate electric field, current density, and magnetic field on the in-plane AMR with a simple physical model, which is based on the in-plane magnetic field induced shift of the spin-momentum locked topological two surface states that are coupled through side surfaces and bulk weak antilocalization (WAL). The large, tunable and bipolar in-plane AMR in BSTS devices provides the possibility of fabricating more sensitive logic and magnetic random access memory AMR devices.

On the Evaluation of Gate Dielectrics for 4H-SiC Based Power MOSFETs

This work deals with the assessment of gate dielectric for 4H-SiC MOSFETs using technology based two-dimensional numerical computer simulations. Results are studied for variety of gate dielectric candidates with varying thicknesses using well-known Fowler-Nordheim tunneling model. Compared to conventional SiO2as a gate dielectric for 4H-SiC MOSFETs, high-kgate dielectric such as HfO2reduces significantly the amount of electric field in the gate dielectric with equal gate dielectric thickness and hence the overall gate current density. High-kgate dielectric further reduces the shift in the threshold voltage with varying dielectric thicknesses, thus leading to better process margin and stable device operating behavior. For fixed dielectric thickness, a total shift in the threshold voltage of about 2.5 V has been observed with increasing dielectric constant from SiO2(k=3.9) to HfO2(k=25). This further results in higher transconductance of the device with the increase of the dielectric constant from SiO2to HfO2. Furthermore, 4H-SiC MOSFETs are found to be more sensitive to the shift in the threshold voltage with conventional SiO2as gate dielectric than high-kdielectric with the presence of interface state charge density that is typically observed at the interface of dielectric and 4H-SiC MOS surface.

Specific features of the switch-on gate current and different switch-on modes in silicon carbide thyristors

The specific features of the temperature and bias dependences of the switch-on gate current in SiC thyristors are examined analytically for two possible switching mechanisms. The so-called γ-mechanism, which is highly typical of the conventional Si thyristors, is characterized by very weak temperature and bias dependences. By contrast, the so-called α-mechanism, which is very characteristic of SiC thyristors, is highly sensitive to changes in temperature and bias. If the thyristor is switched on by the α-mechanism, the switch-on gate current density decreases very steeply with increasing temperature. As a result, the thyristor can lose its working capacity at elevated temperatures due to the instability against even very weak impacts. With decreasing the bias voltage Ua, the gate switch-on current increases very steeply, which can make switching the thyristor on difficult. The unintentional shunting, which is apparently present in high-voltage SiC thyristors, causes the transition from the α- to the γ-mechanism at elevated temperatures and high biases. It can be supposed that introduction of a controllable technological shunting of the emitter–thin base junction allows stabilization of the temperature and bias parameters of SiC thyristors. The analytical results are confirmed by computer simulations performed in wide temperature and bias ranges for a 4H-SiC thyristor of the 18 kV class.

Cover Picture: Atmospheric pressure chemical vapor deposition (APCVD) grown bi‐layer graphene transistor characteristics at high temperature (Phys. Status Solidi RRL 7/2014)

A low-cost and simple atmospheric chemical vapor deposition (APCVD) based double-layer graphene is used to study its transport phenomena at temperature as high as 250 °C. Beyond this temperature the fabricated graphene transistor fails to function, indicating areas of improvements related to dielectric engineering and device isolation. At the same time, it is interesting to note that such low band gap graphene operated fully even at gate current densities as high as 1 A/cm2 and channel current densities as high as 1 MA/cm2 at 250 °C. The study by Ramy M. Qaisi et al. (pp. 621–624) can be a cornerstone to explore graphene as an alternate low-cost material in place of traditional GaN and SiC based power devices for harsh environment application.

A New Method for Enhancing High-$k$/Metal-Gate Stack Performance and Reliability for High-$k$ Last Integration

We show that multistep deposition cum two-step annealing, comprising an ultraviolet ozone (UVO) anneal followed by a low-temperature rapid thermal anneal (RTA), can significantly improve the performance and reliability of a 7.5-Å-equivalent-oxide-thickness (EOT) HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /TiN gate stack, comprising a 25-Å HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> on ~3 Å SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> , i.e., prepared from direct HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> deposition onto an HF-last Si surface. The method yields approximately two orders of magnitude reduction in gate current density and approximately an order of magnitude longer time to breakdown, as compared with the as-deposited gate stack. The observed improvements may be attributed to the “repair” of oxygen-vacancy defects at the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interface and in the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> bulk by the absorbed ozone, through thermal activation provided by the RTA step. The findings provide a promising means for realizing low-leakage and reliable sub-1-nm EOT HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /TiN stacks for high-k last integration.

A thin film triode type carbon nanotube field emission cathode

The field electron emission of carbon nanotubes has been heavily studied over the past two decades for various applications, such as in display technologies, microwave amplifiers, and spacecraft propulsion. However, a commercializable lightweight and internally gated electron source has yet to be realized. This work presents the fabrication and testing of a novel internally gated carbon nanotube field electron emitter. Several specific methods are used to prevent electrical shorting of the gate layer, a common failure for internally gated devices. A unique design is explored where the etch pits extend into the silicon substrate and isotropic etching is used to create a lateral buffer zone between the gate and carbon nanotubes. Carbon nanotubes are self-aligned to and within 10 microns from the gate, which creates large electric fields at low potential inputs. Initial tests confirm high field emission performance with an anode current density (based on total area of the device) of 293 μA cm−2 and a gate current density of 1.68 mA cm−2 at 250 V.

An Efficient Nonlocal Hot Electron Model Accounting for Electron–Electron Scattering

This paper presents a nonlocal model for channel hot electron injection in MOSFETs and nonvolatile memories, which includes a full-band description of optical phonon scattering rates and carrier group velocity. By virtue of its efficient formalism, this model can also include carrier-carrier scattering, which has a marked impact on gate current at low gate voltages. The model is compared against full-band Monte Carlo simulations of typical nor flash devices in terms of distribution functions, bulk current, gate current, and gate current density along the channel. A very good agreement is obtained for various drain and gate voltages and channel lengths.

Electrical Characteristics Analysis at "Oxide Flat-Band Voltage" for Al-SiO2-Si Capacitor

In this paper, a new noun named "oxide flat-band voltage" is proposed meaningfully and further electrical characteristics study focused on non-uniformity in MOS capacitor will be demonstrated. Based on the rectangular barrier approximation, the slope of the ln[Jg@Vox,fb] versus oxide thickness plot of -12.18 is much closer to the theoretical slope of -12.42 than the slope of the ln[Jg@Vfb] versus oxide thickness plot of -11.09. It is because that there are some negative charges existing in the SiO2 dielectrics during the film-grown anodization system resulting in the non-uniformity phenomenon. Furthermore, various device areas of MOS capacitor were designed to do an advanced non-uniformity study. Both in the analysis of differential J-V curves and the slope of natural log of gate current density versus oxide thickness plot, it indicates evidently and identically that the larger the gate electrode area, the worse uniform the dielectric is.

On the accuracy of current TCAD hot carrier injection models in nanoscale devices

In this work, the hot electron injection models presently available for technology support have been investigated within the context of the development of advanced embedded non-volatile memories. The distribution functions obtained by these models (namely the Fiegna Model – FM [1], the Lucky Electron Model – LEM [2] and the recently implemented Spherical Harmonics Expansion of the Boltzman’s Transport Equation – SHE [3]), have been systematically compared to rigorous Monte Carlo (MC) results [4], both in homogeneous and device conditions. Gate-to-drain current ratio and gate current density simulation has also been benchmarked in device simulations. Results indicate that local models such as FM, can partially capture the channel hot electron injection, at the price of model parameter adjustments. Moreover, at least in the device and field condition considered in this work, an overall better agreement with MC simulations has been obtained using the 1st order SHE, even without any particular fitting procedure. Extending the results presented in [3] by exploring shorter gate lengths and addressing the floating gate voltage dependence of the gate current, this work shows that the SHE method could contribute to bridge the gap between the rigorous but time consuming MC method and less rigorous but suitable TCAD local models.