Breakdown Analysis of Magnetic Flip-Flop With 28-nm UTBB FDSOI Technology

Abstract

Dielectric breakdown behaviors of high-performance nonvolatile magnetic flip-flop (NV-MFF) are investigated in this paper. Hybrid magnetic-CMOS flip-flop is implemented based on the spin torque transfer magnetic tunnel junction (MTJ) and 28-nm ultrathin body and buried oxide fully depleted silicon-on-insulator (FDSOI) technology. Transistor high- $\kappa$ metal-gate dielectric stacks and MTJ oxide barrier (MgO) are impacted by time-dependent oxide breakdown, which is shown by circuit-level characterizations: soft-breakdown as performance fluctuation/degradation and hard-breakdown as functional failure. We present the cumulative distribution of breakdown probability of both FDSOI CMOS transistors and MTJ devices. The traditional ohmic breakdown model is applied to evaluate circuit sensitivity to breakdown events. A quantitative analysis is performed considering the breakdown spots in the NV-MFF circuit. The increased gate current density $(\Delta I_{g}/WL)$ aggravates breakdown severity. Simulation results demonstrate both soft and hard breakdown behaviors in different building blocks, e.g., latency degradation in sense amplifier and output level degradation in other digital circuits. Results show that the oxide breakdown in the NV-MFF circuit is in accordance with the weakest link characteristic, as well as the area dependence.